• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.8-13
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• 2009

In this paper, discontinuous interconnect lines are modeled as a cascaded line composed of many uniform interconnect lines. The system functions of respective uniform interconnect lines are determined, followed by its time domain response. Since the time domain response expression is a transcendental form, the waveform expression is reconfigured as an approximated linear expression. The proposed model has less than 2% error in the delay estimation.

• 전자공학회지
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• 제24권12호
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• pp.52-68
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• 1997

• 전기학회논문지
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• 제60권8호
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• pp.1547-1554
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• 2011

As process parameters scale, interconnect width are reduced rapidly while the current flowing through interconnects does not decrease in a proportional manner. This effect increases current density in metal interconnects which may result in poor reliability. Since RMS(root-mean-square) current limits are used to evaluate self-heating and short-time stress failures caused by high-current pluses, RMS current estimation is very important to guarantee the reliability of semiconductor systems. Hence, it is critical to estimate the current limits through interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast, yet accurate RMS current estimation technique that can offer a relatively precise estimate by using closed-form equations. The efficiency and accuracy of the proposed method have been verified through simulations using HSPICE for a vast range of interconnect parameters.

• 대한전자공학회논문지SD
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• 제41권4호
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• pp.101-112
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• 2004

본 논문에서는 3차원 인터커넥트(3D interconnect) 구조를 해석하기 위하여 ADI-유한차분시간영역(ADI-FDTD: Alternating Direction Implicit Finite Difference Time Domain)법으로 맥스웰 회전 방정식(Maxwell's curl equation)을 계산하는 수치 해석 모델을 개발하였고, 개발한 ADI-유한차분시간영역법을 이용하여 3.3 V CMOS 기술로 설계된 샘플러 회로의 일부의 영역에 대해 컴퓨터 모의 실험 결과하여 입력된 구형 전압 신호가 금속 배선을 거치면서 5∼10 ps의 신호 지연과 0.1∼0.2 V의 신호 왜곡이 발생되는 것을 확인하였다. 결론적으로 ADI-유한차분시간영역법을 이용한 풀-웨이브 해석을 통하여 고속의 VLSI 인터커넥트에서의 전자기 현상을 정확하게 분석할 수 있음을 제시하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권3호
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• 대한전자공학회논문지
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• 제23권4호
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• pp.543-549
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• 1986

A topologically based interconnection routing of multilayer printed circuit boards has been proposed. This study focuses on modeling the relative positioning of the interconnect paths rather than absolute positioning within a fixed coordinate system, thereby avoiding simplifications that impose restrictin on the path shapes.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권1호
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• pp.15-22
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• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

• 대한전자공학회논문지SD
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• 제39권8호
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• pp.52-63
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• 2002

본 논문에서는 3차원 인터커넥트(3-D interconnect) 구조를 해석하기 위하여 ADI-유한차분시간영역(ADI-FDTD, Alternating Direction Implicit Finite Difference Time Domain)방법으로 맥스웰 회전방정식(Maxwell's curl equation)을 계산하는 수치 해석 모델을 개발하였다. 3차원 인터커렉트 모델내의 전자기파 문제를 해석하기 위하여 맥스웰 회전 방정식을 ADI-유한차분시간영역방법으로 이산화 하였으며, ADI-유한차분시간영역의 경계에서 발생하는 반사파를 해결하기 위하여 흡수 경계 조건인 완전 정합 층 방법(PML, Perfectly Matched Layer)을 도입하였다. 개발한 ADI-유한차분시간영역방법 및 완전 정합 층의 수치 모델을 검증하기 위하여 3차원 마이크로스트립 전송선(microstrip transmission line) 구조를 3차원 그리드(grid) 구조로 모델링한 후, 시간영역에서 전계 분포를 컴퓨터로 모의 실험하였다. 그리고 본 논문에서 제안한 ADI-유한차분시간영역방법과 종래의 스탠다드 유한차분시간영역방법의 수치적 성능을 정량적으로 비교, 분석하였다.

• 한국자동차공학회논문집
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• 제13권6호
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• pp.48-55
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• 2005

In this paper, a mathematical model and a simulation method for the response time analysis of Local Interconnect Network(LIN) based network systems are proposed. Network-induced delays in a network based control system can vary widely according to the transmission time of message and the overhead time of transmission. Therefore, in order to design a distributed control system using LIN network, a method to predict and verify the timing behavior of LIN protocol is required at the network design phase. Furthermore, a simulation environment based on a timing model of LIN protocol is beneficial to predict the timing behavior of LIN. The model equation is formulated with six timing parameters deduced from timing properties of LIN specification. Additionally, LIN conformance test equations to verify LIN device driver are derived with timing constraints of the parameters. The proposed model equation and simulation method are validated with a result that is measured at real LIN based network system.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.229-236
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• 2005

This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.