• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.6
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• pp.38-48
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• 1993

A recessed n-p Juction diode with the self-aligned sturcture is proposed and fabricated by using the polysilicon as an n$^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar divice and the n$^{+}$ polysilicone mitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition. As$^{+}$ dose for the doping of the polysilicon and the annealing condition using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS and the electrical characteristics are analyzed in terms of the ideality factor of diode (n), contact resistance and reverse leakage current. In addition, n$^{+}$-p junction diodes are formed by using the amorphous silicon (of combination of amorphous and polysiliocn) instead of polysilicon and their characteristics are compared with those of the standard sample. The As$^{+}$ dose for the formation of good junction is about 1~2${\times}10^{16}cm^{2}$ at given RTA conditions (1100.deg. C, 10sec).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.05a
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• pp.152-153
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• 1994

A recessed $n^{+}$-p junction diode with the serf-aligned structure is proposed and fabricated by using the polysilicon as an $n^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar device and the $n^{+}$ polysilicon emitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition $As^{+}$ dose for the doping of the polysilicon, and the annealing using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS. The eleotrical characteristics are analyzed in trims of the ideality factor of diode (n), contact resistance arid reverse leakage current. The $As_{+}$ dose for the formation of good junction is current. The $As^{+}$ dose for the formation of goodjunctions is about 1∼2${\times}$$10^{16}$$cm^{-2}$ at given RTA condition ($1100^{\circ}C$, 10 sec). The $n^{+}$-p structure is successfully applied to the self-aligned bipolar device adopting a single polysilicon technology.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.471.2-471.2
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• 2014

We demonstrate here that an improvement in precursor film density (green density) leads to a great enhancement in the photovoltaic performance of CuInSe2 (CISe) thin film solar cells fabricated with Cu-In nanoparticle precursor films via chemical solution deposition. A cold-isostatic pressing (CIP) technique was applied to uniformly compress the precursor film over the entire surface (measuring 3~4 cm2) and was found to increase its relative density (particle packing density) by ca. 20%, which resulted in an appreciable improvement in the microstructural features of the sintered CISe film in terms of lower porosity, reduced grain boundaries, and a more uniform surface morphology. The low-bandgap (Eg=1.0 eV) CISe PV devices with the CIP-treated film exhibited greatly enhanced open-circuit voltage (VOC, from 0.265 V to 0.413 V) and fill factor (FF, from 0.34 to 0.55), as compared to the control devices. As a consequence, an almost 3-fold increase in the average power conversion efficiency, 3.0 to 8.2% (with the highest value of 9.02%), was realized without an anti-reflection coating. A diode analysis revealed that the enhanced VOC and FF were essentially attributed to the reduced reverse saturation current density (j0) and diode ideality factor (n). This is associated with the suppressed recombination, likely due to the reduction in recombination sites such as grain/air surfaces (pores), inter-granular interfaces, and defective CISe/CdS junctions in the CIP-treated device. From the temperature dependences of VOC, it was confirmed that the CIP-treated devices suffer less from interface recombination.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.362-366
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• 2018

Silicon carbide is widely used in power semiconductor devices owing to its high energy gap. In particular, Schottky barrier diode (SBD) and PiN diodes fabricated on 4H-SiC wafers are being applied to various fields such as power devices. The characteristics of SBD and PiN diodes can be extracted from C-V and I-V characteristics. The measured Schottky barrier height (SBH) was 1.23 eV in the temperature range of 298~473 K, and the average ideal factor is 1.17. The results show that the device with the Schottky contact is characterized by the theory of thermal emission. As the temperature increases, the parameters are changed and the Vth is shifted to lower voltages.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.59-65
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• 2012

A study on the electrical characteristic analysis of solar cell diodes under experimental conditions of varying temperature and frequency has been conducted. From the current-voltage (I-V) measurements, at the room temperature, we obtained the ideality factor (n) for Space Charge Region (SCR) and Quasi-Neutral Region (QNR) of 3.02 and 1.76, respectively. Characteristics showed that the value of n (at SCR) decreases with rising temperature and n (at QNR) increases with the same conditions. These are due to not only the sharply increased SCR current flow but the activated carrier recombination in the bulk region caused by defects such as contamination, dangling bonds. In addition, from the I-V measurements implemented to confirm the junction uniformity of cells, the average current dispersion was 40.87% and 10.59% at the region of SCR and QNR, respectively. These phenomena were caused by the pyramidal textured junction structure formed to improve the light absorption on the device's front surface, and these affect to the total diode current flow. These defect and textured junction structure will be causes that solar cell diodes have non-ideal electrical characteristics compared with general p-n junction diodes. Also, through the capacitance-voltage (C-V) measurements under the frequency of 180 kHz, we confirmed that the value of built-in potential is 0.63 V.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.422-448
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• 1996

Low-temperature epitaxial growth of Si and SiGe layers of Si is one of the important processes for the fabrication of the high-speed Si-based heterostructure devices such as heterojunction bipolar transistors. Low-temperature growth ensures the abrupt compositional and doping concentration profiles for future novel devices. Especially in SiGe epitaxy, low-temperature growth is a prerequisite for two-dimensional growth mode for the growth of thin, uniform layers. UHV-ECRCVD is a new growth technique for Si and SiGe epilayers and it is possible to grow epilayers at even lower temperatures than conventional CVD's. SiH and GeH and dopant gases are dissociated by an ECR plasma in an ultrahigh vacuum growth chamber. In situ hydrogen plasma cleaning of the Si native oxide before the epitaxial growth is successfully developed in UHV-ECRCVD. Structural quality of the epilayers are examined by reflection high energy electron diffraction, transmission electron microscopy, Nomarski microscope and atomic force microscope. Device-quality Si and SiGe epilayers are successfully grown at temperatures lower than 600℃ after proper optimization of process parameters such as temperature, total pressure, partial pressures of input gases, plasma power, and substrate dc bias. Dopant incorporation and activation for B in Si and SiGe are studied by secondary ion mass spectrometry and spreading resistance profilometry. Silicon p-n homojunction diodes are fabricated from in situ doped Si layers. I-V characteristics of the diodes shows that the ideality factor is 1.2, implying that the low-temperature silicon epilayers grown by UHV-ECRCVD is truly of device-quality.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.492-499
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• 2013

We have investigated the electrical properties of Ru/Ni/n-GaN Schottky structure using current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height (${\Phi}_{bo}$) and ideality factor (n) of Ru/Ni/n-GaN Schottky structure are found to be 0.66 eV and 1.44, respectively. The ${\Phi}_{bo}$ and the series resistance ($R_S$) obtained from Cheung's method are compared with modified Norde's method, and it is seen that there is a good agreement with each other. The energy distribution of interface state density ($N_{SS}$) is determined from the I-V measurements by taking into account the bias dependence of the effective barrier height. Further, the interface state density $N_{SS}$ as determined by Terman's method is found to be $2.14{\times}10^{12}\;cm^{-2}\;eV^{-1}$ for the Ru/Ni/n-GaN diode. Results show that the interface state density and series resistance has a significant effect on the electrical characteristics of studied diode.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.236-236
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• 2010

단일접합 $n^+-p/p^+$ (p-emitter) 및 $p^+-n/n^+$ (n-emitter) GaAs 태양전지 (Solar Cell)를 각각 제작하여, 그 소자특성을 비교 분석하였다. AM 1.5 (1 sun, $100\;mW/cm^2$) 표준광을 조사할 경우, p-emitter/n-emitter 소자의 개방회로전압 (Voc), 단락회로전류 (Jsc), 충전율 (FF), 효율 (Eff)은 각각 0.910/0.917 V, $15.9/16.1\;mA/cm^2$, 78.7/78.9, 11.4/12.1%로서, n-emitter 소자가 다소 크지만 거의 비슷한 값을 가지고 있었다. 태양전지의 집광 특성을 분석하기 위하여 조사광의 출력에 따른 태양전지의 소자 특성을 측정하였다. 조사광 강도가 높아짐에 따라 p-emitter 소자의 특성은 점진적으로 증가하는 반면, n-emitter는 1.3 sun에서 약 1.4 배의 최대 효율 (17%)을 나타내고 조사광이 더 증가함에 따라 급격히 감소하는 특성을 보여 주었다. (그림 참고) 본 연구에서 사용한 2종류 소자의 층구조는 서로 반대되는 대칭구조로서, 모두 가까이에 위치하고 있는 표면전극 (surface finger) 방향으로 소수전하 (minority carrier)가 이동하고 다수전하 (majority carrier)는 기판 (두께 $350\;{\mu}m$)을 통한 먼 거리의 후면전극 (back electrode)으로 표류 (drift)되도록 설계되어 있다. 이때, n-emitter에서는 이동도 (mobility)와 확산길이 (diffusion length)가 높은 전자가 후면전극으로 이동하기 때문에 적정밀도의 전자-정공 쌍 (EHP)이 여기될 경우에는 Jsc와 Eff가 극대화되지만, 조사광 강도 또는 EHP가 더 높아질 경우에는 직렬저항의 증가와 함께 전류-전압 (I-V)의 이상인자 (ideality factor)가 커짐으로서 FF와 효율이 급격히 감소한 결과로 분석된다. 현재 전산모사를 통한 자세한 분석을 진행하고 있으며, 본 결과는 효율 극대화를 위한 최적 층구조 및 도핑 밀도 설계에 활용할 수 있을 것으로 판단된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.818-824
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• 2006

The effects of high-temperature process required to fabricate the SiC devices on the surface morphology and the electrical characteristics were investigated for 4H-SiC Schottky diodes. The 4H-SiC diodes without a graphite cap layer as a protection layer showed catastrophic increase in an excess current at a forward bias and a leakage current at a reverse bias after high-temperature annealing process. Moreover it seemed to deviate from the conventional Schottky characteristics and to operate as an ohmic contact at the low bias regime. However, the 4H-SiC diodes with the graphite cap still exhibited their good electrical characteristics in spite of a slight increase in the leakage current. Therefore, we found that the graphite cap layer serves well as the protection layer of silicon carbide surface during high-temperature annealing. Based on a closer analysis on electric characteristics, a conductive surface transfiguration layer was suspected to form on the surface of diodes without the graphite cap layer during high-temperature annealing. After removing the surface transfiguration layer using ICP-RIE, Schottky diode without the graphite cap layer and having poor electrical characteristics showed a dramatic improvement in its characteristics including the ideality factor[${\eta}$] of 1.23, the schottky barrier height[${\Phi}$] of 1.39 eV, and the leakage current of $7.75\{times}10^{-8}\;A/cm^{2}$ at the reverse bias of -10 V.

• Korean Journal of Materials Research
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• v.28 no.5
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• pp.268-272
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• 2018

An $Al_2O_3/AlN$ bilayer deposited on GaN by atomic layer deposition (ALD) is employed to prepare $Al_2O_3/AlN/GaN$ metal-insulator-semiconductor (MIS) diodes, and their interfacial properties are investigated using X-ray photoelectron spectroscopy (XPS) with sputter etch treatment and current-voltage (I-V) measurements. XPS analyses reveal that the native oxides on the GaN surface are reduced significantly during the early ALD stage, indicating that AlN deposition effectively clelans up the GaN surface. In addition, the suppression of Al-OH bonds is observed through the ALD process. This result may be related to the improved device performance because Al-OH bonds act as interface defects. Finally, temperature dependent I-V analyses show that the barrier height increases and the ideality factor decreases with an increase in temperature, which is associated with the barrier inhomogeneity. A Modified Richardson plot produces the Richardson constant of $A^{**}$ as $30.45Acm^{-2}K^{-2}$, which is similar to the theoretical value of $26.4Acm^{-2}K^{-2}$ for n-GaN. This indicates that the barrier inhomogeneity appropriately explains the forward current transport across the $Au/Al_2O_3/AlN/GaN$ interface.