• Title/Summary/Keyword: ISRC

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Implementation of Neuromorphic System with Si-based Floating-body Synaptic Transistors

  • Park, Jungjin;Kim, Hyungjin;Kwon, Min-Woo;Hwang, Sungmin;Baek, Myung-Hyun;Lee, Jeong-Jun;Jang, Taejin;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.2
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    • pp.210-215
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    • 2017
  • We have developed the neuromorphic system that can work with the four-terminal Si-based synaptic devices and verified the operation of the system using simulation tool and printed-circuit-board (PCB). The symmetrical current mirrors connected to the n-channel and p-channel synaptic devices constitute the synaptic integration part to express the excitation and the inhibition mechanism of neurons, respectively. The number and the weight of the synaptic devices affect the amount of the current reproduced from the current mirror. The double-stage inverters controlling delay time and the NMOS with large threshold voltage ($V_T$) constitute the action-potential generation part. The generated action-potential is transmitted to next neuron and simultaneously returned to the back gate of the synaptic device for changing its weight based on spike-timing-dependent-plasticity (STDP).

Supperession of Short Channel Effects in 0.1$\mu\textrm{m}$ nMOSFETs with ISRC Structure (짧은 채널 효과의 억제를 위한 ISRC (Inverted-Sidewall Recessed-Channel)구조를 갖는 0.1$\mu\textrm{m}$ nMOSFET의 특성)

  • 류정호;박병국;전국진;이종덕
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.34D no.8
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    • pp.35-40
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    • 1997
  • To suppress the short channel effects in nMOSFET with 0.1.mu.m channel length, we have fabricated and characterized the ISRC n MOSFET with several process condition. When the recess oxide thickness is 100nm and the channel dose for threshold voltge adjustment is 6*10$^{12}$ /c $m^{-2}$ , B $F_{2}$$^{+}$, the maximum transconductance at $V_{DS}$ =2.0V is 455mS/mm and the BIDL is kept within 67mV. By comparing the ISRC n MOSFET with the conventioanl SHDD (shallowly heavily dopped drain) nMOSFET, we verify the suppression of short channel effects ISRC structure.e.

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Thin-film passivation of the polymer EL device using parylene and its application to the passive matrix PELD system

  • Lee, Cheon-An;Jin, Sung-Hun;Jung, Keum-Dong;Lee, Jong-Duk;Park, Byung-Gook
    • 한국정보디스플레이학회:학술대회논문집
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    • 2004.08a
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    • pp.669-672
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    • 2004
  • The thin-film passivation technology using the poly-para-xylylene (parylene) was applied to polymer electroluminescent devices. The fabricated device shows a good luminescent characteristic of maximum 11640 cd/$m^2$. The measured lifetime was reached up to 28 hours, which means the effectiveness of the passivation. Applying the parylene thin-film passivation technique, 10${\times}$10 passive matrix display system was implemented and obtained some still images.

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A New I-V Equation for Thin Film Transistors and Its Parameter Extraction Method

  • Jung, Keum-Dong;Kim, Yoo-Chul;Park, Byung-Gook;Shin, Hyung-Cheol;Lee, Jong-Duk
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.201-204
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    • 2008
  • Based on the device physics, a new I-V equation for TFTs is derived and a simple parameter extraction method is suggested. The new method gives more physically meaningful threshold voltage and mobility, and the obtained values can be directly used for the TFT device modeling.

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Pentacene OTFTs with $Al_2O_3$ gate insulator by Atomic Layer Deposition Process

  • Jin, Sung-Hun;Kim, Jin-Wook;Lee, Cheon-An;Park, Byung-Gook;Lee, Jong-Duk
    • 한국정보디스플레이학회:학술대회논문집
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    • 2003.07a
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    • pp.15-18
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    • 2003
  • Pentacene OTFTs of $Al_2O_3$ insulator treated with a diluted PMMA were fabricated for the application of the low voltage operation and large area displays. The operation voltage of 15 V and the mobility of 0.35 $cm^2/Vsec$ are obtained even adopting the thick dielectric of 100 nm which was deposited by atomic layer deposition at the temperature of $150^{\circ}C$. The current on-off ratio was $4.1{\times}10^4$ for the OTFTs treated with 9:1 PMMA and good saturation characteristics were obtained as drain voltage increases.

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Application of Area-Saving RF Test Structure on Mobility Extraction

  • Lee, Jae-Hong;Kim, Jun-Soo;Park, Byung-Gook;Lee, Jong-Duk;Shin, Hyung-Cheol
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.2
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    • pp.98-103
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    • 2009
  • An RF test structure is proposed and its applicability is confirmed by measuring DC characteristics and high frequency characteristics. Effective mobility extraction is also performed to confirm the validity of proposed test structure. The area of suggested test structure consumed on wafer was decreased by more than 50% and its characteristics do not be degraded compared with conventional structure.

Analytic Threshold Voltage Model of Recessed Channel MOSFETs

  • Kwon, Yong-Min;Kang, Yeon-Sung;Lee, Sang-Hoon;Park, Byung-Gook;Shin, Hyung-Cheol
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.1
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    • pp.61-65
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    • 2010
  • Threshold voltage is one of the most important factors in a device modeling. In this paper, analytical method to calculate threshold voltage for recessed channel (RC) MOSFETs is studied. If we know the fundamental parameter of device, such as radius, oxide thickness and doping concentration, threshold voltage can be obtained easily by using this model. The model predicts the threshold voltage which is the result of 2D numerical device simulation.

Partially Homomorphic Encryption HW accelerator (부분적 동형암호 HW 가속기 설계에 관한 연구)

  • Nam, Kevin;Chang, Jiwon;Cho, Myunghyun;Bang, Inyoung;Paek, Yunheung
    • Proceedings of the Korea Information Processing Society Conference
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    • 2020.05a
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    • pp.268-271
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    • 2020
  • 최근 동형암호에 대한 관심이 높아진 가운데, 이를 활용한 Cloud Computing 서비스를 구축하기 위한 시도가 이어지고 있다. 기존 동형암호 HW에 대한 연구는 수학적 기능 구현 자체에 중점을 두고 있다. 본 논문에서는 동형암호 CNN inference 모델 설계 과정에서 HW 구현 한계점과 bottleneck들을 수학적 기법이 아닌 HW 특징을 이용해서 극복하는 과정을 서술하였다.

Modeling of pentacene MIS capacitors with admittance measurements and the effects of dispersive charge transport

  • Jung, Keum-Dong;Lee, Cheon-An;Park, Dong-Wook;Park, Byung-Gook;Shin, Hyung-Cheol;Lee, Jong-Duk
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.67-69
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    • 2006
  • Capacitance and loss values of pentacene MIS capacitors with different thicknesses are measured as a function of frequency for the modeling of the devices. The equivalent circuit for the ideal MIS capacitor is adopted to model the obtained admittance, so the values of $C_i,\;C_d,\;C_b$, and $R_b$ are determined for each pentacene thickness. In the loss curve, broader loss peaks are observed in measurement than the modeling results regardless of the pentacene thickness. By considering the effects of dispersive charge transport in bulk semiconductor, more accurate modeling results are obtained.

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Micro-tissue collecting tool for diagnosis of micro-spike biopsy (마이크로 스파이크로 채취한 조직의 진단을 위한 미세 조직회수도구)

  • Jeong, Hyo-Young;Koo, Kyo-In;Lee, Sang-Min;Ban, Jae-Won;Park, Ho-Soo;Bang, Seoung-Min;Song, Si-Young;Cho, Dong-Il Dan
    • Journal of Sensor Science and Technology
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    • v.18 no.2
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    • pp.122-127
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    • 2009
  • We have developed and reported several micro-spikes for minimally invasive biopsy. In this paper, a micro-tissue collecting tool for tissue diagnosis extracted by micro-spike is presented. Using proposed polydimethy-siloxane (PDMS) micro-tissue collecting tool, which has a negative micro-spike structure in a porous chamber, the extracted tissue in a micro-spike is effectively detached. The gastro-intestinal tissue of a pig is extracted in an in vivo environment, and then it is detached from a micro-spike using the PDMS micro-tissue collecting tool. A fine clinical picture of the detached tissue is acquired.