• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.109-109
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• 2003

III- V ferromagnetic semiconductor has attracted great attention as a potential application for spintronics due to a successful demonstration of spin injection from ferromagnetic GaNnAs into semiconductor. GaMnN may be one of the possible candidates for room temperature operation. Samples were grown on sapphire (0001) substrate at $650^{\circ}C$ via molecular beam epitaxy with a single Precursor of (Et$_2$Ga(N$_3$)NH$_2$$CH_3$) and solid source of Mn at different Mn source temperature. The background pressure is low 10$^{-10}$ Torr and the samples growth pressure was 1.4 $\times$ 10$^{-6}$ Torr.

• 대한전자공학회논문지
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• 제21권5호
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• pp.11-16
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• 1984

본 논문에서는 III-V족 반도체 소자의 제작에 사용되는 액상 에피층 성장 시스템의 제작 및 이를 이용한 AIGaAs/GaAs 이중 헤테로 구조의 성장 방법에 관하여 고찰하였다. 또한 이 헤테로 구조가 발광 다이오드에 이용될 수 있음을 확인하였다.

• 한국전기전자재료학회논문지
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• 제16권12S호
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• pp.1187-1194
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• 2003

A BCl$_3$/Ne plasma chemistry was used to etch Ga-based (GaAs, AIGaAs, GaSb) and In-based (InGaP, InP, InAs and InGaAsP) compound semiconductors in a Planar Inductively Coupled Plasma (ICP) reactor. The addition of the Ne instead of Ar can minimize electrical and optical damage during dry etching of III-V semiconductors due to its light mass compared to that of Ar All of the materials exhibited a maximum etch rate at BCl$_3$ to Ne ratios of 0.25-0.5. Under all conditions, the Ga-based materials etched at significantly higher rates than the In-based materials, due to relatively high volatilities of their trichloride etch products (boiling point CaCl$_3$ : 201 $^{\circ}C$, AsCl$_3$ : 130 $^{\circ}C$, PCl$_3$: 76 $^{\circ}C$) compared to InCl$_3$ (boiling point : 600 $^{\circ}C$). We obtained low root-mean-square(RMS) roughness of the etched sulfate of both AIGaAs and GaAs, which is quite comparable to the unetched control samples. Excellent etch anisotropy ( > 85$^{\circ}$) of the GaAs and AIGaAs in our PICP BCl$_3$/Ne etching relies on some degree of sidewall passivation by redeposition of etch products and photoresist from the mask. However, the surfaces of In-based materials are somewhat degraded during the BCl$_3$/Ne etching due to the low volatility of InCl$_{x}$./.

• 센서학회지
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• 제29권4호
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• pp.266-269
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• 2020

In this study, we investigated the effect of a sulfur passivation (S-passivation) process step on the electrical properties of surface-channel In_0.7Ga_0.3As quantum-well (QW) metal-oxide-semiconductor field-effect transistors (MOSFETs) with S/D regrowth contacts. We fabricated long-channel In_0.7Ga_0.3As QW MOSFETs with and without (NH₄)₂S treatment and then deposited 1/4 nm of Al₂O₃/HfO₂ through atomic layer deposition. The devices with S-passivation exhibited lower values of subthreshold swing (74 mV/decade) and drain-induced barrier lowering (19 mV/V) than the devices without S-passivation. A conductance method was applied, and a low value of interface trap density D_it (2.83×10¹² cm^-2eV^-1) was obtained for the devices with S-passivation. Based on these results, interface traps between InGaAs and high-κ are other defect sources that need to be considered in future studies to improve III-V microsensor sensing platforms.

• Advances in nano research
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• 제2권4호
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• pp.211-217
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• 2014

The self-assembled strain-induced sub-micrometric islands and nanostructures are grown from In-As-Sb-P quaternary liquid phase on InAs (100) substrates in Stranski-Krastanow growth mode. Two samples are under consideration. The first sample consists of unencapsulated islands and lens-shape quantum dots (QDs) grown from expressly inhomogeneous liquid phase. The second sample is an n-InAs/p-InAsSbP heterostructure with QDs embedded in the p-n junction interface. The morphology, size and shape of the structures are investigated by high-resolution scanning electron (SEM) and transmission electron (TEM) microscopy. It is shown that islands, as they decrease in size, undergo shape transitions. Particularly, as the volume decreases, the following succession of shape transitions are detected: sub-micrometric truncated pyramid, {111} facetted pyramid, {111} and partially {105} facetted pyramid, completely unfacetted "pre-pyramid", hemisphere, lens-shaped QD, which then evolves again to nano-pyramid. A critical size of $5{\pm}2nm$ for the shape transformation of InAsSbP-based lens-shaped QD to nano-pyramid is experimentally measured and theoretically evaluated.

• 공업화학
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• 제30권4호
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• pp.504-508
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• 2019

GaInP/AlGaInP 이종접합 구조를 제안하고 집광 조건에서 가장 높은 효율을 달성한 III-V 화합물 반도체 다중접합 태양전지의 맨 위 subcell에 주로 사용되는 GaInP 동종접합 구조를 대체해 이종접합 구조가 응용될 가능성에 대하여 조사하였다. $2^{\circ}$ off 된 웨이퍼와 $10^{\circ}$ off 된 서로 다른 off-cut 방향을 갖는 두 종류의 GaAs 기판 위에 성장된 태양전지의 특성을 집광 조건에서 측정하고 비교하였다. $10^{\circ}$ off 된 태양전지에서 더 높은 단락전류와 변환효율을 얻었다. 1 sun 조건에서 $10^{\circ}$ off 된 기판 위에 제작된 $2{\times}2mm^2$ 면적의 태양전지에서 $9.21mA/cm^2$의 단락전류밀도와 1.38 V의 개방 전압이 측정되었다. $10^{\circ}$ off 기판 위에 제작된 $5{\times}5mm^2$ 태양전지에서 집광도 증가에 따라 곡선인자(fiill factor)가 감소하여 변환효율은 6.03% (1 sun)에서 5.28% (20 sun)로 측정되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.728-735
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• 2016

A 70 MHz temperature-compensated on-chip CMOS relaxation oscillator for mobile display driver ICs is proposed to reduce frequency variations. The proposed oscillator compensates for frequency variation with respect to temperature by adjusting the bias currents to control the change in delay of comparators with temperature. A bandgap reference (BGR) is used to stabilize the bias currents with respect to temperature and supply voltages. Additional temperature compensation for the generated frequency is achieved by optimizing the resistance in the BGR after measuring the output frequency. In addition, a trimming circuit is implemented to reduce frequency variation with respect to process. The proposed relaxation oscillator is fabricated using 45 nm CMOS technology and occupies an active area of $0.15mm^2$. The measured frequency variations with respect to temperature and supply voltages are as follows: (i) ${\pm}0.23%$ for changes in temperature from -30 to $75^{\circ}C$, (ii) ${\pm}0.14%$ for changes in $V_{DD1}$ from 2.2 to 2.8 V, and (iii) ${\pm}1.88%$ for changes in $V_{DD2}$ from 1.05 to 1.15 V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권4호
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• pp.295-301
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• 2008

Recently, the demand on mm-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the mm-wave frequency band have been traditionally implemented in III-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled mm-wave circuits realized in a Si CMOS technology. In this work, a 58 GHz CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a $0.13-{\mu}m$ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the mm-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 GHz with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 dBc/Hz at 5 MHz offset was achieved. The output power varied around -20 dBm over the measured tuning range. The circuit drew current (including buffer current) of 10 mA from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 dBc/Hz.

• 한국통신학회논문지
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• 제11권3호
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• pp.153-163
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• 1986

III-V족 복합물 반도체인 GaAs를 이용한 초고속소자는 DBS(Direct Broadcast Satellite), 광통신, microwave 및 digital 집적회로에 널리 사용되낟. 이와 같은 GaAS를 substrate재료로 D/E MESFET'S을 이용한 4Kx4bit SRAM, HEMT'S에 의한 4K bit SRAM과 X-band용 수신기전단부의 MMIC화가 보고되였고, 3차원적인 광집적회로의 연구도 가까운 장래에 완성될 것이다. 본 논문에서는 현재까지 널리 사용되어온 GaAs반도체 재료, 제조공정기술, 소자응용과 집적회로 설계면을 고찰 검토한다. 마지막으로 초고속소자의 전망을 논의한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.283-287
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• 2017

Recently, Ni-InGaAs has been required for high-performance III-V MOSFETs as a promising self-aligned material for doped source/drain region. As downscaling of device proceeds, reduction of contact resistance ($R_c$) between Ni-InGaAs and n-InGaAs has become a challenge for higher performance of MOSFETs. In this paper, we compared three types of sample, vacuum, 2% $H_2$ and 4% $H_2$ annealing condition in rapid thermal annealing (RTA) step, to verify the reduction of $R_c$ at Ni-InGaAs/n-InGaAs interface. Current-voltage (I-V) characteristic of metal-semiconductor contact indicated the lowest $R_c$ in 4% $H_2$ sample, that is, higher current for 4% $H_2$ sample than other samples. The result of this work could be useful for performance improvement of InGaAs n-MOSFETs.