• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.998-1001
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• 2009

A new flexible TFT backplane structure with improved mechanical reliability is proposed. Amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistors based on this structure have been fabricated on a polyimide substrate, and the resultant mechanical durability has been evaluated in a cyclic bending test. The panel can withstand 10,000 bending cycles at a bending radius of 5 mm without any noticeable TFT degradation. After 10K bending cycles, the change of threshold voltage, mobility, sub-threshold slope, and gate leakage current were only -0.22V, -0.13$cm^2$/V-s, -0.05V/decade, and $-3.05{\times}10^{-13}A$, respectively.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.443-443
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• 2012

We fabricated a-IGZO TFT with AZO/Ag/AZO transparent multilayer source/drain contacts by rf magnetron sputtering. Enhanced electrical device performance of a-IGZO TFT with AZO/Ag/AZO multilayer S/D electrodes (W/L = = 400/50 mm) was achieved with a subs-threshold swing of 3.78 V/dec, a minimum off-current of 10-12 A, a threshold voltage of 1.80 V, a field effect mobility of 10.86 cm2/Vs, and an on/off ration of 9x109. It demonstrated the potential application of the AZO/Ag/AZO film as a promising S/D contact material for the fabrication of the high performance TFTs.

• 한국전기전자재료학회논문지
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• 제27권10호
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• pp.648-652
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• 2014

We have investigated the effect of electrical properties of amorphous InGaZnO thin film transistors (a-IGZO TFTs) by post thermal annealing in $O_2$ ambient. The post-annealed in $O_2$ ambient a-IGZOTFT is found to be more stable to be used for oxide-based TFT devices, and has better performance, such as the on/off current ratios, sub-threshold voltage gate swing, and, as well as reasonable threshold voltage, than others do. The interface trap density is controlled to achieve the optimum value of TFT transfer and output characteristics. The device performance is significantly affected by adjusting the annealing condition. This effect is closely related with the modulation annealing method by reducing the localized trapping carriers and defect centers at the interface or in the channel layer.

• 전기학회논문지
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• 제66권4호
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• pp.721-726
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• 2017

We fabricated stretchable thin-film transistors(TFTs) on a polydimethylsiloxane substrate with patterned polyimide island structures by using an amorphous InGaZnO semiconductor and parylene gate insulator. The TFTs exhibited a field- effect mobility of $5cm^2V^{-1}s^{-1}$ and a current on/off ratio of $10^5$ at a relatively low operating voltage. Furthermore, the fabricated transistors showed no noticeable changes in their electrical performance for large strains of up to 50 %.

• 한국산학기술학회논문지
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• 제10권7호
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• pp.1489-1496
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• 2009

비정질 인듐-갈륨-아연 산화물 박막트랜지스터를 모델링 하여서, 능동층의 구조, 두께, 평형상태의 전자밀도에 대응하는 박막트랜지스터의 특성을 연구하였다. 단일 능동층 박막트랜지스터의 경우, 능동층이 얇을 때 높은 전계효과이동도를 보였다. 문턱전압의 절대값은 능동층의 두께가 20 nm일 때 최저치를 보였으며, 문턱전압이하 기울기는 두께에 대한 의존성을 보이지 않았다. 복층구조 능동층의 경우, 하부의 능동층이 높은 평형상태 전자밀도를 가질 때보다 우수한 스위칭 특성을 보였다. 이 경우에도 능동층의 두께가 얇을 때에 높은 전계효과 이동도를 보였다. 높은 평형상태 전자밀도의 능동층의 두께를 증가시키면 문턱전압은 음의 방향으로 이동하였다. 문턱전압이하 기울기는 능동층의 구조에 대하여 특별한 의존성을 보이지 않았다. 이상과 같은 데이터는 산화물반도체 박막트랜지스터 능동층의 구조, 두께, 도핑비율을 최적화함에 효과적으로 사용될 것으로 기대된다.

• Journal of Information Display
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• 제12권4호
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• pp.209-212
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• 2011

The threshold voltage shift (${\Delta}V_{th}$) under positive-voltage bias stress (PBS) of InGaZnO (IGZO) thin-film transistors (TFTs) annealed at different temperatures in air was investigated. The dramatic degradation of the electrical performance was observed at the sample that was annealed at $700^{\circ}C$. The degradation of the saturation mobility (${\mu}_{sat}$) resulted from the diffusion of indium atoms into the interface of the IGZO/gate insulator after crystallization, and the degradation of the subthreshold slope (S-factor) was due to the increase in the interfacial and bulk trap density. In spite of the degradation of the electrical performance of the sample that was annealed at $700^{\circ}C$, it showed a smaller ${\Delta}V_{th}$ under PBS conditions for $10^4$ s than the samples that were annealed at $500^{\circ}C$, which is attributed to the nanocrystal-embedded structure. The sample that was annealed at $600^{\circ}C$ showed the best performance and the smallest ${\Delta}V_{th}$ among the fabricated samples with a ${\mu}_{sat}$ of $9.38cm^2/V$ s, an S-factor of 0.46V/decade, and a ${\Delta}V_{th}$ of 0.009V, which is due to the passivation of the defects by high thermal annealing without structural change.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.450-450
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• 2012

In recent days, advances in ZnO-based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). In particular, the development of high-mobility ZnO-based channel materials has been proven invaluable; thus, there have been many reports of high-performance TFTs with oxide semiconductor channels such as ZnO, InZnO (IZO), ZnSnO (ZTO), and InGaZnO (IGZO). The reliability of oxide TFTs can be improved by examining more stable oxide channel materials. In the present study, we investigated the effects of an ALD-deposited water vapor permeation barrier on the stability of ZnO and HfZnO (HZO) thin film transistors. The device without the water vapor barrier films showed a large turn-on voltage shift under negative bias temperature stress. On the other hand, the suitably protected device with the lowest water vapor transmission rate showed a dramatically improved device performance. As the value of the water vapor transmission rate of the barrier films was decreased, the turn-on voltage instability reduced. The results suggest that water vapor related traps are strongly related to the instability of ZnO and HfZnO TFTs and that a proper combination of water vapor permeation barriers plays an important role in suppressing the device instability.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1203-1207
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• 2008

For a large sized, ultra definition (UD) and high refresh rate for motion blur free AMLCD TVs, amorphous IGZO thin film transistor (TFT) are applied and investigated in terms of threshold voltage ($V_{th}$) shift influenced by active layer thickness uniformity, source drain etching technology, heat treatment and passivation condition. Optimizing above parameters, we fabricated the world's largest 15 inch XGA AMLCD successfully.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.170-170
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• 2012

최근 주목받고 있는 amorphous InGaZnO (a-IGZO) thin film transistors (TFTs)는 수소가 첨가된 비정질 실리콘 TFT (a-Si;H)에 비해 비정질 상태에서도 높은 이동도와 뛰어난 전기적, 광학적 특성에 의해 큰 주목을 받고 있다. 또한 넓은 밴드갭에 의해 가시광 영역에서 투명한 특성을 보이고, 플라스틱 기판 위에서 구부러지는 성질에 의해 플랫 패널 디스플레이나 능동 유기 발광 소자 (AM-OLED), 투명 디스플레이에 응용되고 있다. 하지만, 실제 디스플레이가 동작하는 동안 스위칭 TFT는 백라이트 또는 외부에서 들어오는 빛에 지속적으로 노출되게 되고, 이 빛에 의해서 TFT 소자의 신뢰성에 악영향을 끼친다. 또한, 디스플레이가 장시간 동안 동작 하면 내부 온도가 상승하게 되고 이에 따른 온도에 의한 신뢰성 문제도 동시에 고려되어야 한다. 특히, 실제 AM-LCD에서 스위칭 TFT는 양의 게이트 전압보다 음의 게이트 전압에 의해서 약 500 배 가량 더 긴 시간의 스트레스를 받기 때문에 음의 게이트 전압에 대한 신뢰성 평가는 대단히 중요한 이슈이다. 스트레스에 의한 문턱 전압의 변화는 게이트 절연막과 반도체 채널 사이의 계면 또는 게이트 절연막의 벌크 트랩에 의한 것으로 게이트 절연막의 선택에 따라서 신뢰성을 효과적으로 개선시킬 수 있다. 본 연구에서는 적층된 $Si_3N_4/SiO_2$ (NO 구조) 이중층 구조를 게이트 절연막으로 사용하고, 완충층의 역할을 하는 $SiO_2$막의 두께에 따른 소자의 전기적 특성 및 신뢰성을 평가하였다. a-IGZO TFT 소자의 전기적 특성과 신뢰성 평가를 위하여 간단한 구조의 pseudo-MOS field effect transistor (${\Psi}$-MOSFET) 방법을 이용하였다. 제작된 소자의 최적화된 $SiO_2$ 완충층의 두께는 20 nm이고 $12.3cm^2/V{\cdot}s$의 유효 전계 이동도, 148 mV/dec의 subthreshold swing, $4.52{\times}10^{11}cm^{-2}$의 계면 트랩, negative bias illumination stress에서 1.23 V의 문턱 전압 변화율, negative bias temperature illumination stress에서 2.06 V의 문턱 전압 변화율을 보여 뛰어난 전기적, 신뢰성 특성을 확인하였다.