Annealing temperature dependence on the positive bias stability of IGZO thin-film transistors

The threshold voltage shift (${\Delta}V_{th}$) under positive-voltage bias stress (PBS) of InGaZnO (IGZO) thin-film transistors (TFTs) annealed at different temperatures in air was investigated. The dramatic degradation of the electrical performance was observed at the sample that was annealed at $700^{\circ}C$. The degradation of the saturation mobility (${\mu}_{sat}$) resulted from the diffusion of indium atoms into the interface of the IGZO/gate insulator after crystallization, and the degradation of the subthreshold slope (S-factor) was due to the increase in the interfacial and bulk trap density. In spite of the degradation of the electrical performance of the sample that was annealed at $700^{\circ}C$, it showed a smaller ${\Delta}V_{th}$ under PBS conditions for $10^4$ s than the samples that were annealed at $500^{\circ}C$, which is attributed to the nanocrystal-embedded structure. The sample that was annealed at $600^{\circ}C$ showed the best performance and the smallest ${\Delta}V_{th}$ among the fabricated samples with a ${\mu}_{sat}$ of $9.38cm^2/V$ s, an S-factor of 0.46V/decade, and a ${\Delta}V_{th}$ of 0.009V, which is due to the passivation of the defects by high thermal annealing without structural change.