• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.304-307
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• 2013

Reverse engineering of semiconductor devices utilizes delayering processes, in order to identify how the interconnection lines are stacked over transistor gates. Cu metal has been used in recent fabrication technologies, and de-processes becomes more difficult with the shrinking device dimensions. In this article, reverse engineering technologies to reveal the Cu interconnection lines and Cu via-plugs embedded in dielectric layers are investigated. Stacked dielectric layers are removed by $CF_4$ plasma etching, then the exposed planar Cu metal lines and via-plugs are selectively delineated by wet chemical solution, instead of the commonly used plasma-based dry etch. As a result, we have been successful in extracting the layouts of multiple layers within a system IC, and this technique can be applicable to other logic IC, analog IC, and CMOS IC, etc.

• Proceedings of the Korean Vacuum Society Conference
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• 1997.02a
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• pp.45-46
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• 1997

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.278-285
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• 2012

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-kHz signal bandwidth and oversampling ratio (OSR) of 64, thus a $3^{rd}$-order ${\Delta}{\Sigma}$ modulator operating at 1 MH was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-${\mu}m$ CMOS mixed-mode process, and occupied $0.86{\times}1.33mm^2$. The measurement results shows suppressed DC power under about -30 dBFS with minimized device flicker noise.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.1-10
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• 1997

It is well-known that rectangular bulk-Si sensors prepared by etch or epi etch-stop micromachining technology are already in practical use today, but the conventional bulk-Si sensor shows some drawbacks such as large chip size and limited applications as silicon sensor device is to be miniaturized. We consider a circular-shape SOI(Silicon-On-Insulator) micro-cavity technology to facilitate multiple sensors on very small chip, to make device easier to package than conventional sensor like pressure sensor and to provide very high over-pressure capability. This paper demonstrates the cross-functional results for stress analyses(targeting $5{\mu}m$ deflection and 100MPa stress as maximum at various applicable pressure ranges), for finding permissible diaphragm dimension by output sensitivity, and piezoresistive sensor theory from two-type SOI structures where the double SOI structure shows the most feasible deflection and small stress at various ambient pressures. Those results can be compared with the ones of circular-shape bulk-Si based sensor$^{[17]}. The SOI micro-cavity formed the sensors is promising to integrate with calibration, gain stage and controller unit plus high current/high voltage CMOS drivers onto monolithic chip.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2002.05a
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• pp.1039-1042
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• 2002

SMD(Surface Mounting Device) which mounts electronic components as IC-Chips on PCB automatically, produces a large dynamic force and vibration. The unwanted vibrations in SMD degrade the performance of the precision device and it is the major obstacle to limit its speed for mounting. This study investigated the vibration analysis of a typical SMD to predict the natural frequencies and mode shapes. To validate the finite element analysis of SMD, the FE result was compared with that of ODS measurements. It was shown that the predicted results were well correlated with the experimental modal parameters.

• Proceedings of the Korea Society for Simulation Conference
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• 1999.10a
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• pp.272-277
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• 1999

The necessity of voice recording device was increased using voice signal IC with designed LSI/VLSI. The control unit which developed here voice recorder has low power dissipation, portable, and comfortable using voice source. However, the Korea voice recorder abilities far behind of foreign products for its performance and size on sailing. So we used Chua circuit to improvement voice quality abilities after minimize power supply device and circuit by designing voice recording device into lower power dissipation power circuit.

• Electrical & Electronic Materials
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• v.9 no.5
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• pp.512-517
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• 1996

본 고는 반도체 재료가 갖는 자기효과를 이용하여 자기센서의 종류 및 특성등에 대하여 서술하였다. 반도체 LSI의 응용분야가 확대됨에 따라서 반도체 센서를 이용한 극소형화, 고성능화, 저가격화, 다기능화등이 가능하게 되었다. 이러한 상황에서 반도체를 이용한 홀 소자나 자기저항 소자와 같은 자기센서 등을 주변회로와 일체화시킨 초소형 시스템에 대한 연구가 활발하다. 특히 화합물 반도체는 자기센서에 적합한 물리적인 특성을 갖고 있기 때문에, 자기센서로 효율을 나타내고 있다. 반도체의 미세가공기술의 발전과 LSI제조기술의 발전을 이용하여 센서의 집적화, 저가격화를 가능하게 하였으며, 다른 종류의 반도체 센서들을 자기센서와 함께 하나의 칩위에 장착할 수 있는 응용집적센서(Application-specific Integrated Sensor)가 더욱 중요한 역할을 할 것이다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.34-41
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• 1998

In this paper, I designed a P1394 serial bus chip as new bus interface architecture which can transmit the multimedia data at the rate of 400 Mbps and guarantee necessary bandwidth. because multimedia data become meaningless data after appropriate time, it is necessary to transfer multimedia data in real time, P1394 serial bus chip designed in this paper support isochronous transfer mode to solve this problem. Also, designed P1394 serial bus chip can transfer high quality video data or high quality audio data because it support the speed of 400 Mbps. While user must set device ID manually in previous interface such as SCSI, device ID is automatically determined if user connect each node with designed P1394 serial bus cable and power on. To design this chip, I verified the behavioral of the entrire system and synthesized layout. Also, I did layout the analog blocks and blocks which must be optimized in full custom.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.1
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• pp.149-152
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• 2017

This paper investigated the method for the output of power management IC (PMIC) for BLE beacon with energy harvesting device to be maintained constantly. The capacitor was used to store the energy supplied from energy harvesting device such as solar module and the capacitance was estimated to the optimum value according to the interval for the BLE beacon to send advertising signal.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.