• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.9-14
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• 2005

This paper reports the hot carrier induced RF performance degradation of bulk dynamic threshold voltage MOSFET (B-DTMOS) compared with bulk MOSFET (B-MOS). In the normal and moderate mode operations, the degradations of cut-off frequency $(f_{T})$ and minimum noise figure $(F_{min})$ of B-DTMOS are less significant than those of B-MOS devices. Our experimental results show that the RF performance degradation is more significant than the U performance degradation after hot carrier stressing. Also, the degradation characteristics of RF power Performance of B-DTMOS due to hot carrier effects are measured for the first time.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1065-1070
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• 2007

The effects of hot carriers and self-heating on the electrical stability of p-channel TFTs have been analysed combining experimental data and numerical simulations. While hot carrier effects were shown not to induce appreciable degradation, self-heating related instability was found to more seriously affect the device characteristics. New models have been developed to explain the reported results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.9
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• pp.683-686
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• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1367-1369
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• 1998

To achieve the ULSI goals of higher density, greater performance and operation speed have been scaled down. However, the reduction of channel length cause undesirable problems such as drop of punchthrough voltage, hot-carrier degradation and high leakage current, etc.. It is shown that the device characteristics depend on process parameters. In this Paper, we catched hold of trends of hot-carrier effects and punchthrough voltages due to variation of some process parameters such as LDD doses(P), spacer lengths, channel doses($BF_2$) and $V_T$ adjusting channel implantation energies using design trend curve (DTC). As the LDD and channel doses increased, hot-carrier phenomena became more severe, and punchthrough voltage was decreased. It were represented that punchthrough and hot carrier effects were critically depend on LDD and channel doses.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.266-269
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• 1997

Hot carrier effects as a function of bias stress time and bias stress conditions were syste-matica1ly investigated in p-channel po1y-Si TFT's fabricated on the quartz substrate. The device degradation was observed for the negative bias stress. After positive bias stressing, Improvement of electrical characteristic except for subthreshold slope was observed. It was found that these results were related to the hot carrier injection into the gate oxide and interface states at the poly-Si/SiO$_2$interface rather than defects states generation under bias stress.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.7
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• pp.23-29
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• 1997

The performance degradation of CMOS differential amplifiers due to hot carrier effect has been measured and analyzed. Two-state CMOS amplifiers whose input transistors are PMOSFETs were designed and fabriacted using the ISRC CMOS 1.5.mu.m process. It was observed after the amplifier was hot-carrier stressed that the small-signal voltage gain and the input offset voltage increased and the phase margin decreased. The performance variation results from the increase of the transconductances and gate capacitances of the PMOSFETs used as input transistors in the differential input stage and the output stage and also resulted from the decrease of their output conductances. After long-term stress, the amplifier became unstable. The reason might be that its phase margin was reduced due to hot carrier effect.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.433-436
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• 1998

Hot carrier induceed the performance degradation of sense amplifier circuit in DRAM has been measured and analyzed using 0.8.mu.m CMOS process. Simulation and experimental results show that the degradation of the MOS devices affects the decrease of the half-Vcc, voltage gain and the increase of the sensing voltage gain and the increase of the sensing voltage. The dominant degradation mechanism is the capacitance imblance in the bit-line pair. We carried out the spice simulation to investigate the degradation of the sense amplifier circuit.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.130-138
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• 1996

The size of a device needs to scale down to increase its integrity and speed. As the size of the device is reduced, the hot-carrier degradation that severely effects on device reliabilty is concerned. In this paper, sub-micron buried-channel P-MOSFETs were fabircated, and the hot-carrier effects were invetigated. Also the hot-carrier effect in the buired-channel P-MOSFETs and the surface-channel P-MOSFETs were compared with simulation programs using SUPREM-4 and MINIMOS-4. This paper showed that the electric characteristics of sub-micron P-MOSFET are different from those of N-MOSFET. Also it showed that the punchthrough voltage ( $V_{pt}$ ) was abruptly drop after applying the stress and became almost 0V when the channel lengths were shorter than 0.6.mu.m. The lower punchthrough voltage causes the device to operte poorly by the deterioration of cut-off characteries in the switching mode. We can conclude that the buried channel P-MOSFET for CMOS circuits has a limit of the channel length to be around 0.6.mu.m.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.105-112
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• 1993

Oxide and reoxidized-nitrided-oxide were formed by furnace oxidation and rapid thermal processing (RTP). MOS capacitor and n-MOSFET's with those films as gate insulators were fabricated. The electrical characteristics of insulators were evaluated by current-voltage, high-frequency capacitance-voltage (C-V), and time-dependent dielectrical breakdown (TDDB) measurements. The hot carrier effects of MOSFET's were also investigated. Time-dependent dielectrical breakdown (TDDB) characteristics show that the life time of reoxidized-nitrided-oxide films is about 3 times longer than that of oxides. Hot carrier effects reveal that the life time of MOSFET's with reoxidized-nitrided-oxides is about 3 times longer than that of MOSFET's with oxides. Therefore, it is found that the reliability of dielectric films estimated by the hot carrier effects of MOSFET's is consistent with that of dielectric films from TDDB method.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.93-102
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• 1994

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.