• Electrical & Electronic Materials
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• v.10 no.1
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• pp.26-32
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• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.349-352
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• 2004

The $CdS_{1-x}Se_x$ thin films were grown on the GaAs(100) wafers by a Hot Wall Epitaxy method(HWE). The temperatures the source and the substrate temperature are $580^{\circ}C\;and\;440^{\circ}C$ respectively. The crystalline structure of thin films was investigated by double crystal X-tay diffraction(DCXD). Hall effect on the sample was measured by the van der Pauw method and studied on the carrier density and mobility dependence on temperature. In order to explore the applicability as a photoconductive cell, we measured the sensitivity($\gamma$), the ratio of photocurrent to darkcurrent(pc/dc), maximum allowable power dissipation(MAPD), spectral response and response time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.29-30
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• 2005

Experimental results are presented for the degradation of 3 nm-thick gate oxide ($SiO_2$) under both Negative-bias Temperature Instability(NBTI) and Hot-carrier-induced(HCI) stresses using P and NMOSFETs that are annealed with hydrogen or deuterium gas at high-pressure (1~5 atm.). Statistical parameter variations depend on the stress conditions. We suggest that deuterium bonds in $SiO_2$ film is effective in suppressing the generation of traps related to the energetic hot electrons.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.21-30
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• 2012

Technology trend and application of laser fuse, anti-fuse, and eFUSE as well as the structure, programming mechanism, and reliability of eFUSE have been reviewed. In order to ensure eFUSE reliability in the field, a sensing circuit trip point consistent with the fuse resistance distribution, process variation, and device degradation in the circuit such as hot carrier or NBTI, as well as fuse resistance reliability must be considered to optimize and define a reliable fuse programming window.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.429-432
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• 1998

The impact of hot carrier induced gate leakage current on the refresh time of memory devices has been examined. The maximum allowable supply voltage for cell transistor has been determined form the degradation of the refresh time. The desing guideline for cell capacitors and refresh circuits has been suggested.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1101-1104
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• 2003

In this paper, we analyzed the gate current and substrate current by the hot carrier effects and restoration phenomenon of characteristics by time in the p-channel MOSFETs. The Stress voltage condition is a voltage in maximum gate current and time is 3s, 10s, 30s, l00s, 1000s, 2000s and 3000s. As results of analysis, the gate current and substrate current were decreased by stress time, and the restoration time of characteristics were shown the results that were decreased by the exponential times.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.515-518
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• 2002

In this paper, we demonstrate the impact of oxide interface-state on low temperature poly-Si TFTs. The TFTs with interface-state exhibit poor performance and serious degradation under hot carrier and gate bias stress. Our results indicate that the worse oxide integrity cause initial characteristic shift and device instability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.489-492
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• 1999

The effects of alternate bias stress on p-channel poly-Si TPT's has been systematically investigated. It has been shown that the application of alternate bias stress affects device degradation for the negative bias stress as well as device improvement for the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ under bias stress.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.149-149
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• 2016

Ceramic is widely known material due to its outstanding mechanical property. Besides, Zirconia(ZrO2) has a low thermal conductivity so it is advantage in a heat insulation. Because of these superior properties, ZrO2 is attracted to many fields using ultra high temperature for example vehicle engines, aerospace industry, turbine, nuclear system and so on. However brittle fracture is a disadvantage of the ZrO2. In order to overcome this problem, we can make the ceramic materials to the forms of ceramic nanoparticles, ceramic nanowhiskers and these forms can be used to an agent of composite materials. In this work, we selected Au catalyzed Vapor-Liquid-Solid mechanism to synthesize ZrO2 nanowhiskers. The ZrO2 whiskers are grown through Hot-wall Chemical Vapor Deposition(Hot wall CVD) using ZrCl4 as a powder source and Au film as a catalyst. This Hot wall CVD method is known to comparatively cost effective. The synthesis condition is a temperature of $1100^{\circ}C$, a pressure of 760torr(1atm) and carrier gas(Ar) flow of 500sccm. To observe the morphology of ZrO2 scanning electron microscopy is used and to identify the crystal structure x-ray diffraction is used.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.46-52
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• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.