The effect of GIDL and SILC on the performance degradation of the refresh circuit in DRAM

GIDL과 SILC가 DRAM refresh 회로의 성능저하에 미치는 영향

The impact of hot carrier induced gate leakage current on the refresh time of memory devices has been examined. The maximum allowable supply voltage for cell transistor has been determined form the degradation of the refresh time. The desing guideline for cell capacitors and refresh circuits has been suggested.