• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.489-492
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• 1999

The effects of alternate bias stress on p-channel poly-Si TPT's has been systematically investigated. It has been shown that the application of alternate bias stress affects device degradation for the negative bias stress as well as device improvement for the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ under bias stress.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1301-1304
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• 2007

We have investigated degradation of short channel n-type poly-Si TFTs with LDD under high gate and drain voltage stress due to self-heating. We have found that the threshold voltage of short channel TFT is shifted to negative direction on the selfheating stress, whereas the threshold voltage of long channel is moved to positive direction.

• ETRI Journal
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• v.28 no.2
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• pp.253-256
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• 2006

We propose a novel power metal oxide semiconductor field effect transistor (MOSFET) employing a strained-Si channel structure to improve the current drivability and on-resistance characteristic of the high-voltage MOSFET. A 20 nm thick strained-Si low field channel NMOSFET with a $0.75\;{\mu}m$ thick $Si_{0.8}Ge_{0.2}$ buffer layer improved the drive current by 20% with a 25% reduction in on-resistance compared with a conventional Si channel high-voltage NMOSFET, while suppressing the breakdown voltage and subthreshold slope characteristic degradation by 6% and 8%, respectively. Also, the strained-Si high-voltage NMOSFET improved the transconductance by 28% and 52% at the linear and saturation regimes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.1-5
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• 2010

In this paper, we directly compare the program efficiency of conventional channel hot electron (CHE) injection methods and a novel hot electron injection methods using substrate forward biases in our silicon-oxide-nitride-oxide-silicon (SONOS) cell. Compared with conventional CHE injection methods, the proposed injection method showed improved program efficiency including faster program operation at lower bias voltages as well as localized trapping features for multi-bit operation with a threshold voltage difference of 1 V at between the forward and reverse read. This program method is expected to be useful and widely applied for future nano-scale multi-bit SONOS memories.

• Journal of Semiconductor Engineering
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• v.3 no.2
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• pp.161-167
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• 2022

Electrical characteristics of LDMOS power device with LDD(Lightly Doped Drain) structure is studied with variation of the region of channel and LDD. The channel in LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of CMOS inverter. Two-dimensional TCAD MEDICI simulation is used to study hot-carrier effect, on-resistance Ron, breakdown voltage, and transient switching characteristic. The voltage-transfer characteristics and on-off switching properties are studied as a function of the channel length and doping levels. The digital logic levels of the output and input voltages are analyzed from the transfer curves and circuit operation. Study indicates that drain current significantly depends on the channel length rather than the LDD region, while the switching transient time is almost independent of the channel length. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.30 no.4
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• pp.175-185
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• 2018

This research investigates the internal flow and heat transfer in a plate heat exchanger with chevron shape by utilizing the computational fluid dynamics (CFD) software. The basic unit of the plate heat exchanger is generally composed of a hot channel, an intermediate chevron plate, and a cold channel. Several studies have reported experimental and numerical simulation of heat transfer and pressure drop. This study focused on the detailed numerical simulation of flow and heat transfer in the complicated chevron shape channel. The long chevron plate was designed to include 16 chevron patterns. For proper mesh resolution, the number of cells was determined after the grid sensitivity test. The working fluid is water, and its properties are defined as a function of temperature. The Reynolds number ranges from 900 to 9,000 in the simulation. A realizable $k-{\varepsilon}$ model and non-equilibrium wall function are properly considered for the turbulent flow. The friction factors and heat transfer coefficient are validated by comparing them with existing empirical correlations, and other patterned flow phenomena are also investigated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.120-131
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• 2007

A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (T-gate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal work-function and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

• Design & Manufacturing
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• v.2 no.1
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• pp.45-50
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• 2008

Micro channel is to fabricate desired pattern on the polymer substrate by pressing the patterned mold against the substrate which is heated above the glass transition temperature, and it is a high throughput fabrication method for bio chip, optical microstructure, etc. due to the simultaneous large area patterning. However, the bad pattern fidelity in large area patterning is one of the obstacles to applying the hot embossing technology for mass production. In the present study, stamper of cross channel with width $100{\mu}m$ and height $50{\mu}m$ was manufactured using UV-LiGA process. Micro channel was manufactured using stamper manufactured in this study. Also replicability appliance was evaluated for micro channel and factors affected replicability were investigated using Taguchi method.

• Nuclear Engineering and Technology
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• v.40 no.2
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• pp.139-146
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• 2008

This paper presents two of the fuel channel designs being considered for the CANDU-SCWR, a pressure-tube type supercritical water cooled reactor. The first is an insulated pressure tube design. The pressure tube is thermally insulated from the hot coolant by a porous ceramic insulator. Each pressure tube is in direct contact with the moderator, which operates at an average temperature of about $80^{\circ}C$. The low temperature allows zirconium alloys to be used. A perforated metal liner protects the insulator from being damaged by the fuel bundles and erosion by the coolant. The coolant pressure is transmitted through the perforated metal liner and insulator and applied directly to the pressure tube. The second is a re-entrant design. The fuel channel consists of two concentric tubes, and a calandria tube that separates them from the moderator. The coolant enters between the annulus of the two concentric fuel channel tubes, then exits the fuel channel through the inner tube, where the fuel bundles reside. The outer tube bears the coolant pressure and its temperature will be the same as the coolant inlet temperature, ${\sim}350^{\circ}C$. Advantages and disadvantages of these designs and the material requirements are discussed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.36-45
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• 1993

The n-channel MOSFETs with gate-$n^{-}$S/D overlapped structure have been fabricated by ITLDD(inverse-T gate lightly doped drain) technology. The gate length(L$_{mask}$) was 0.8$\mu$m. The degradation effects of hot carriers injected into the gate oxide were analyzed in terms of threshold voltage, transconductance and drain current variations. The degradation dependences on the gate voltage and drain voltage were characterized. The devices with higher n-concentration showed higher resistivity against the hot carrier injection. As the results of investigating the lifetime of the device, the lifetime showed longer than 10 years at V$_{d}$ = 5V for the overlapped devices with the implantation of an phosphorus dose of 5$\times$10$^{13}$ cm$^{-2}$ and an energy of 80 keV in the n$^{-}$resion.