• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.228-230
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• 2008

A LLC resonant converter with hold-up time extension technique for computer power supply is proposed. Since the proposed circuit has a current boost-up capability of resonant inductor regardless of the input voltage level and the load power condition, operating near the resonant frequency, it can provide the power to the load as the input voltage drops to half of reflected output voltage to the transformer primary. This extends the hold-up time of computer power supply and improves the system power density and conversion efficiency at nominal input voltage. The experimental results with prototype are given to confirm the validity of the proposed circuit.

• 한국자동차공학회논문집
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• 제9권6호
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• pp.76-84
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• 2001

Generally fuel injection system using solenoid have some problems between control signal and mechanical movement like as time lag. Main purpose of the present study is to help the design optimization of GDSI for real engine application. We have adopted two different solenoid driving circuit, namely saturation and pick-hold type and have investigated experimentally the current, needle force, needle opening duration and injection quantity. The pick-hold type driving circuit surpassed a saturation type in the response time and pression control of injection quantity. Accordingly, Using characterization data of operating factors such as time constant, driving force and so on, can be evaluated and adjusted to obtain an optimum injector performance.

• 한국자동차공학회논문집
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• 제3권6호
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• pp.134-144
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• 1995

The solenoid actuated hydrogen injector and the capacitive peak-hold type driving circuit were designed and made, and the hydrogen supply system for in-cylinder injection was constructed with these. The performance of the injector was investigated through measuring the pintle lift profiles and the injection quantities, and the performance of the hydrogen supply system was confirmed through the experiments at the single cylinder engine. The injection quantity increased linearly as the duration of driving signal increased. At the single cylinder engine, the hydrogen injector was operated stably. The hydrogen flow rate of the injector with the peak-hold type driving circuit could be controlled precisely at high engine speed or low load condition only with the variation of signal duration.

• 전자공학회논문지
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• 제53권10호
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• pp.27-33
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• 2016

본 논문은 초퍼 안정화기법을 적용한 저잡음 증폭기를 제안한다. 초퍼 안정화기법은 CMOS 증폭기의 저주파수 대역 오프셋과 플리커 잡음을 감소시키는 효과적인 기법이다. 기존의 초퍼 증폭기는 초퍼로 인해 발생되는 초핑 스파이크를 제거하기 위해 Low Pass Filter(LPF)를 사용하기 때문에 저항과 커패시터가 큰 면적을 차지한다는 단점을 가지고 있다. 제안된 초퍼 증폭기는 LPF 대신 샘플 앤 홀드 방식의 초핑 스파이크 제거 회로를 사용하여 적은 전압감쇄에서 36%, 면적에서 11%의 이득을 얻을 수 있다.

• 한국자동차공학회논문집
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• 제5권1호
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• pp.174-185
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• 1997

The performance of the solenoid actuated hydrogen injector and the capacitive peak-hold type driving circuit was predicted through the modeling of the injector and the driving circuit the modeling was composed of the driving circuit, the solenoid, the moving parts of the injector, and the hydrogen injection system. The performance of the injector through the modeling was compared with the results of the solenoid and injector rig tests, and those were consistent with each other. Through the prediction of the injector performance, the effects of the components such as electrical resistor, capacitor, and injector spring are easily known to the injector performance required.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.238-246
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• 2011

A 3-5 GHz UWB radar chip in 0.13 ${\mu}m$ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.133-136
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• 2002

This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.

• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.7-13
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• 1997

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns sifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can e applied by scan shifting and then pulsing a system clock like the full scan but with much les scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.

• 전력전자학회논문지
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• 제15권2호
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• pp.96-102
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• 2010

최근 전 세계적인 지구 기후 변화에 따라 에너지를 절약하기 위한 정책이 수립되고 있으며 특히 권고 사양인 CSCI 규제가 점차 강화되고 있어 서버용 전원장치의 효율 조건 역시 높아지고 있다. 이에 따라 서버용 전원 장치의 효율 향상을 얻을 수 있는 기술로서 hold up time extension 기술이 많은 주목을 받아왔다. Hold up time 보상기술은 서버용 전원 장치가 가지는 hold up time 이라는 특징으로 인하여 발생할 수 있는 손실을 추가적인 기술을 통하여 보상함으로서 효율을 높일 수 있는 방법으로 그동안 많은 연구가 이루어져 왔다. 본고에서는 고효율 고밀도 서버용 전원장치를 위한 hold up time 보상회로에 대하여 알아보고자 한다.

• 전기전자학회논문지
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• 제8권1호
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• pp.12-21
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• 2004

오류제어는 많은 전자 시스템의 주요한 관심사이다. 시스템 동작에 영향을 미치는 대부분의 고장은 회로에서 발생하는 타이밍 위반의 결과로 나타나는 비정상적인 신호지연으로 인한 것이며, 이는 주로 과도고장에 의해 발생한다. 본 논문에서는 CMOS 회로의 동작 중에 타이밍 오류를 검출하는 회로를 설계하였다. 타이밍 오류 검출기는 클럭에 의해 제어되는 시스템의 준비시간 및 대기시간의 위반에 대한 오류를 검출할 수 있다. 설계한 회로는 데이터의 입력이 클럭 천이지점에서 변화할 때 과도전류를 측정하여 오류 검출기의 전류 감지회로에서 발생시킨 기준전류와 비교함으로써 오류의 발생 여부를 확인 할 수 있다. 이러한 방법은 클럭에 의해 동작하는 시스템의 준비시간 및 대기시간의 위반에 따른 오류를 효과적으로 검출할 수 있음을 보여준다. 이 회로는 2.5V 공급전압의 $0.25{\mu}m$ CMOS 기술을 이용하여 구현하였으며, HSPICE로 시뮬레이션하여 정당성 및 효율성을 검증하였다.