• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.960-964
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• 2003

In this paper, the CMOS integrated circuit technique for implementing current-mode maximum and minimum operations scheme is described. The maximum and minimum operations are incorporated into the same scheme with parallel processing. Using this scheme as the basic unit, an analog three-input maximum, median, and minimum circuit is designed. The performance of the proposed circuit shows a very sharp transfer characteristic and high accuracy. The proposed circuit achieves a high-speed operation, which is suitable for real-time systems. The PSPICE simulation results demonstrating the characteristic of the proposed circuit are included.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.199-206
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• 2019

Recently, an expansion of safety facilities has been widely applied to effectively manage the safety of train operation due to increase of the high-speed section of the general railway and the introduction of high-speed train. Accordingly, performance improvement, upgrading and high reliability of existing safety devices are required. the dragging detector, one of the safety devices, is an analogue system that consists of closed circuit with an electric current flows and operates when the closed circuit is opened by the impact of the dragging object. Such method has unreasonable problem that should be replaced after being detected. It is need to replace with an automatic return type dragging detector which is easy to maintain. In addition, it is necessary to develop a dragging detector that applicable to general railway and urban railway including high-speed railway, in accordance with the speeding up and densification of trains, although it is currently applied only to high-speed railway. In this paper, we propose an automatic return type dragging detector which has versatility and excellent maintainability with digital sensor and real time monitoring.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.925-928
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• 1993

In this paper the caracteristics of the fuzzy flip-flop which was proposed as a fuzzy sequential circuit is firstly mentioned. Secondly the circuit construction of typical fuzzy flip-flip circuits using VHDL (Very high speed integrated circuit Hardware Description Language) compiler and simulator is presented. Finally the possibility of the application of the fuzzy sequential circuit will be mentioned.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• 한국초전도학회:학술대회논문집
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• v.12
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• pp.57-57
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• 2002

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1161-1167
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• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.987-992
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• 2000

In a high speed spindle system, it is very important to monitor the operation of the spindle to prevent catastrophic damage to the system. Widely used sensors for monitoring are eddy-current and capacitive types. These sensors provide high accuracy of monitoring, but their steep prices lead to expensive high speed spindle systems. The main goal of our research is to develop technology for producing high speed spindle system utilizing magnetic bearings. As active magnetic bearings require position sensors for feedback control, a noncontact position sensor is being developed as a part of this main goal. Once developed, it will contribute to affordable high speed spindle system. This paper describes the selection process of the sensor types and the design of the driving circuit. We also report the experimental results that characterize the static and dynamic performances of the inductive sensor.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.2
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• pp.324-328
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• 2012

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.11
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• pp.859-865
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• 1991

The paper proposes a design of high-speed dynamic CMOS PLA (Programmable Logic Array) which performs stable circuit operation. The race problem which nay occur in a NOR-NOR implementation of PLA is free in the proposed dynamic CMOS PLA by delaying time between the clocks to the AND- and to the OR-planes. The delay element has the same structure as the product line of the longest delay in the AND p`ane. Therefore it is unnecessary to design the delay element or to calculate correct delay time. The correct delay generated by the delay element makes the dynamic CMOS PLA to perform correct and stable circuit operation. Theproposed dynamic CMOS PLA has few variation of switching delay with the increasing number of inputs or outputs in PLA. It is verified by SPICE circuit simulation that the proposed dynamic CMOS PLA has the better performance over existing dynamic CMOS PLA's.

• ETRI Journal
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• v.38 no.5
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• pp.903-910
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• 2016

We propose a novel multi-stack (MS) technique for a compact and wideband electromagnetic bandgap (EBG) structure in high-speed multilayer printed circuit boards. The proposed MS technique efficiently converts planar EBG arrays into a vertical structure, thus substantially miniaturizing the EBG area and reducing the distance between the noise source and the victim. A dispersion method is presented to examine the effects of the MS technique on the stopband characteristics. Enhanced features of the proposed MS-EBG structure were experimentally verified using test vehicles. It was experimentally demonstrated that the proposed MS-EBG structure efficiently suppresses the power/ground noise over a wideband frequency range with a shorter port-to-port spacing than the unit-cell length, thus overcoming a limitation of previous EBG structures.