Browse > Article

Hybrid Type Structure Design and DLT-Replacement Circuit of the High-Speed Frequency Synthesizer  

Lee Hun-Hee (Dept. of Electronic Engineering and Research Institute of Computer, Information & Communication, Chungbuk National University)
Heo Keun-Jae (Dept. of Electronic Engineering and Research Institute of Computer, Information & Communication, Chungbuk National University)
Jung Rag-Gyu (Dept. of Electronic Engineering and Research Institute of Computer, Information & Communication, Chungbuk National University)
Ryu Heung-Gyoon (Dept. of Electronic Engineering and Research Institute of Computer, Information & Communication, Chungbuk National University)
Publication Information
The Journal of Korean Institute of Electromagnetic Engineering and Science / v.15, no.12, 2004 , pp. 1161-1167 More about this Journal
Abstract
The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.
Keywords
High Speed Switching; PLL Frequency Synthesizer; Digital Hybrid PLL;
Citations & Related Records
연도 인용수 순위
  • Reference
1 H. G. Ryu, Y. Y. Kim, H. M. Yu, and S. B. Ryu, 'Design of DDFS-driven PLL frequency synthesizer with reduced complexity', IEEE Transactions on Consumer Electronics, vol. 47, no. 1, Feb. 2001
2 David M. Materna, 'A lightweight fast hopping synthesizer for EHF satellite applications', Military Communications Conference, MILCOM 95, Conference Record, IEEE, vol. 2, pp. 752-759, 1995
3 M. A. EI-Ela, 'High speed PLL frequency synthe-sizer with synchronous frequency sweep', NRSC '99. Proceedings of the Sixteenth National, pp. 23-25, Feb. 1999
4 Y. Fouzar, M. Sawan, and Y. Savaria, 'A new fully integrated CMOS phase-locked loop with low jitter and fast lock time', ISCAS 2000 Geneva. The 2000 IEEE International Symposium on Circuits and Systems, vol. 2, pp. 253-256, May 2000