• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.6
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• pp.618-625
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• 2005

This paper has achieved that an optimal design and experiments of heater and cathode of electron gun that serve to embody high current density in CRT display. For the high brightness, high resolution and larger size in CRT display, high current density of electron gun is indispensible. An Impregnation style cathode is used, and must heighten operating temperature of heater to get high current density for this, it is proportional hereupon and power dissipation increases. In this paper, to get low power cathode with high current density, There are produced and tested sample that differ lead type of heater, coating method, the pitch and number of winding of the first and second coiling in the heat emission area for the low power design of high current density cathode heater in this paper.

• Geomechanics and Engineering
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• v.12 no.4
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• pp.595-609
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• 2017

Due to high in-situ stress and brittleness of rock mass, the surrounding rock masses of underground caverns are prone to appear splitting failure. In this paper, a kind of loading-unloading variable elastic modulus model has been initially proposed and developed based on energy dissipation principle, and the stress state of elements has been determined by a splitting failure criterion. Then the underground caverns of Dagangshan hydropower station is analyzed using the above model. For comparing with the monitoring results, the entire process of rock splitting failure has been achieved through monitoring the splitting failure on side walls of large-scale caverns in Dagangshan via borehole TV, micro-meter and deformation resistivity instrument. It shows that the maximum depth of splitting area in the downstream sidewall of the main power house is approximately 14 m, which is close to the numerical results, about 12.5 m based on the energy dissipation model. As monitoring result, the calculation indicates that the key point displacement of caverns decreases firstly with the distance from main powerhouse downstream side wall rising, and then increases, because this area gets close to the side wall of main transformer house and another smaller splitting zone formed here. Therefore it is concluded that the energy dissipation model can preferably present deformation and fracture zones in engineering, and be very useful for similar projects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.532-541
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• 2003

In a memory, most power is dissipated in high capacitive lines such as predecoder lines, word lines, and bit lines. To reduce the power dissipation in these high capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. One is the charge recycling predecoder (CRPD). The second one is the charge recycling word line decoder (CRWD). The last one is the charge sharing bit line (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and word lines. Theoretically, the power consumption in predecoder lines and word lines are reduced to a half. The CSBL reduces the swing voltage in the ROM bit lines to very small voltage using a charge sharing technique. the CSBL can significantly reduce the power dissipation in ROM bit lines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64% of the power of previous ROM designs respectively. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K16bits was fabricated in a 0.3${\mu}{\textrm}{m}$ CMOS process. The CRCS-ROM consumes 8.63㎽ at 100MHz with 3.3V. The chip core area is 0.1 $\textrm{mm}^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.83-90
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• 2004

This paper proposes an efficient scan testing method for compression of test input data and reduction of test power for SOC. The proposed method determines whether some parts of a test response can be reused as a part of next input test data on the analysis of deterministic test data and its response. Our experimental results show that benchmark circuits have a high similarity between un-compacted deterministic input test data and its response. The proposed testing method achieves the average of 29.4% reduction of power dissipation based on the number of test clock and 69.7% reduction of test data for ISCAS'89 benchmark circuits.

• ETRI Journal
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• v.29 no.6
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• pp.785-793
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• 2007

In this paper, we present an integrated rail-to-rail fully differential operational transconductance amplifier (OTA) working at low-supply voltages (1.5 V) with reduced power consumption and showing high DC gain. An embedded adaptive biasing circuit makes it possible to obtain low stand-by power dissipation (lower than 0.17 mW in the rail-to-rail version), while the high DC gain (over 78 dB) is ensured by positive feedback. The circuit, fabricated in a standard CMOS integrated technology (AMS 0.35 ${\mu}m$), presents a 37 V/${\mu}s$ slew-rate for a capacitive load of 15 pF. Experimental results and high values of two quality factors, or figures of merit, show the validity of the proposed OTA, when compared with other OTA configurations.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.253-256
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• 2001

This paper introduces the design of high-speed analog- to-digital converter for high-definition TV, camcorders, portable equipments and implemented in a 0.65${\mu}{\textrm}{m}$ CMOS technology. Key circuits developed for low power and high speed A/D converter are a dynamic comparator that consumes no static power, a source follower buffered op amp that achives wide bandwidth using large input devices. The converter achieves low power dissipation of 40-mW at 3.3-V power supply. Measured performance includes 0.53 LSB of INL and 0.48 LSB of DNL while sampling at 60MHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• Journal of Power Electronics
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• v.7 no.4
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• pp.294-300
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• 2007

This paper deals with a design of a bootstrap power supply using snubber energy regeneration, which is used to power a high-side gate driver of a half-bridge circuit. In the proposed circuit, the energy stored in the low-side snubber capacitor is transferred to the high-side bootstrap capacitor without any magnetic components. Thus, the power dissipation in the RCD snubber can be effectively reduced. The operation principle and design method of the proposed circuit are presented. The experimental results are also provided to show the validity of the proposed circuit.

• Proceedings of the KIEE Conference
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• 2008.10a
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• pp.93-94
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• 2008

Diagnostic tests were performed in three high voltage motors. These tests included insulation resistance, polarization index, ac current, dissipation factor($tan{\delta}$) and partial discharge magnitude. The rewind of motor stator insulation at rated voltage is assessed by the results of these tests. After completing the diagnostic tests, the stator windings of motors were subjected to gradually increasing ac voltage, until the insulation punctured. NO.1 and No.2 motors failed near rated voltage of 14.0 kV, respectively. These motors are lower that expected for good quality coils in 6.6 kV class motors. The breakdown voltage of No.3 motor was 15.0 kV.