• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.707-710
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• 1998

This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.351-354
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• 2011

This paper was carried about thermal analysis for high efficiency point contact solar cell. Therefore, we carried about 2-D device and process simulator according to design and process parameters. As a result of simulations, power transfer efficiency have decreased more increasing temperature. Especially, power transfer efficiency of room temperature have been showed 25%. The other hand, power transfer efficiency of 350 K kalvin temperature have been showed 20%. Therefore, we will considered design with thermal dissipation of device.

• 한국정보통신학회논문지
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• 제25권6호
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• pp.853-856
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• 2021

In this paper, a low noise amplifier having high gain and low noise by using input and inter stage matching circuits has been designed. A current-reused two-stage common-source topology is adopted, which can obtain high gain and low power consumption. Deterioration of noise characteristics according to the source inductive degeneration matching is compensated by adopting additional matching circuits. Moreover trade-offs among noise, gain, linearity, impedance matching, and power dissipation have been considered. In this design, 0.18-mm CMOS process is employed for the simulation. The simulated results show that the designed low noise amplifier can provide high power gain and low noise characteristics.

• 한국전자통신학회논문지
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• 제17권2호
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• pp.351-356
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• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권11호
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• pp.737-741
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• 2000

We fabricated resistive superconducting fault current limiters (SFCL) based on YBCO thin films grown on 2-inch diameter $Al_2O_3$ substrates. Two SFCLs with nearly identical properties were connected in series to investigate simultaneous quench. There was a slight difference in the rate of voltage increase between two SFCL units when they were operated independently. This difference resulted in significantly imbalanced power dissipation between the units. This imbalance was removed by connecting a shunt resister to an SFCL in parallel. The appropriate values of shunt resistance were 80 ${\Omega}$ at 75 $V_rms$ and 110 ${\Omega}$ at 120 $V_rms$, respectively. Increased power input at high voltages also reduced the initial imbalance in power dissipation, but with increase in film temperature to higher than 200 K.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• 한국생산제조학회지
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• 제23권4호
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• pp.355-360
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• 2014

Recently, the use of LED is increasing. This paper presents the new package process of thermal compression bonding using metal layered LED chip for the high power LED device. Effective thermal dissipation, which is required in the high power LED device, is achieved by eutectic/flip chip bonding method using metal bond layer on a LED chip. In this study, the process condition for the LED eutectic die bonder system is proposed by using the analysis program, and some experimental results are compared with those obtained using a DST (Die Shear Tester) to illustrate the reliability of the proposed process condition. The cause of bonding failures in the proposed process is also investigated experimentally.

• 한국전기전자재료학회논문지
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• 제22권10호
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• pp.826-831
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• 2009

In this paper, a high power RF amplifier module using AlN substrate of high thermal conductivity has been proposed. This RF amplifier module has the advantage of compact size and effective heat dissipation for the packaging of high power chip. To fabricate the thru-hole and scribing line on AlN substrate, the key parameters of $CO_2$ laser were experimented. And then, microstrip lines and spiral planar inductors were fabricated on an AlN substrate using the thin-film process. The fabricated microstrip lines on the AlN substrate has an attenuation value of 0.1 dB/mm up to 10 GHz. The fabricated spiral planar inductor has a high quality factor, a maximum of about 62 at 1 GHz for a 5.65 nH inductor. Packaging of a RF power amplifier was implemented on an AlN substrate with thru-hole. From the measured results, the gain is 24 dB from 13 to 15 GHz and the output power is 33.65 dBm(2.3 W).

• 한국통신학회논문지
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• 제37권8A호
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• pp.712-719
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• 2012

본 논문은 오디오 신호 처리 시스템의 저속 고해상도 ADC를 위해 설계된 CMOS 단일비트 3차 델타시그마 변조기를 설계하였다. 변조기 내 적분기에 사용되는 연산증폭기의 전력소모를 감소시키기 위해서 연산증폭기내 바이어스 전류원에 차단/동작 기능을 하는 스위치를 장착시켰다. 또한 변조기내 스위치의 위치를 최적화 하여 기존의 스위칭 방식에서 발생하는 주파수 특성 변화를 최소화하였다. 단일 비트 3차 델타시그마 변조기 구조를 선택하였으며, 제안한 델타 시그마 변조기의 성능측정결과 전원 전압 3.3V, 샘플링 주파수 6.4MHz, 입력주파수 20KHz에서 17.1mW의 전력소모를 나타냈다. SNDR은 84.3dB, 유효비트수는 13.5비트를 나타내었다.