• 반도체디스플레이기술학회지
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• 제22권1호
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• pp.94-98
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• 2023

In the case of high-speed data transmission on high multilayer boards, signal coherence is a problem, especially due to the via hole, and a solution to improve return loss or insertion loss by applying a back drill to the via hole is being proposed. In this paper, Near-Field Electromagnetic measurements were made on a high multilayer board to determine how the presence or absence of back drill affects signal consistency. For this purpose, we used a signal generator, spectrum analyzer, and EMC scanner on a test board to determine if it is possible to distinguish between areas with and without back drill in the via holes of the stubs on the board. Also, we analyzed the measured value of S11, S21 and EMC etc. for how much it improves the signal attenuation of the stub with back drill. Through this, we knew that less electromagnetic waves are generated the stub via with back drill. At future research, we will analyze how much it improves the signal loss and electromagnetic waves due to the depth of back drill.

• Journal of electromagnetic engineering and science
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• 제2권2호
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• pp.68-74
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• 2002

In this paper, a pre-layout design approach for high-speed microprocessor is proposed. For multilayer PCB stark up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system. The system model includes VRM, decoupling capacitors, multiple power and ground planes for core voltage, vias, as well as microprocessor. Finally, the simulation results are verified by measurements data.

• 전자공학회논문지S
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• 제34S권11호
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• pp.34-42
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• 1997

In this paper, we show an optimal structure of impedance control in high density layouts ina high multilayers PCB. The impedance control in a high multilayers FR-4 PCB is very portant isue because a dielectric layer's thickness is very thin. Especially, odd mode impedance control is more difficult than characteristic impedance control in high multilayers PCB. So, we show an optimal structure of odd mode impedance control in that dielectric thickness is about 0.1mm with limited state and discuss multilayers PCB's for swich circuti pack and backplane in developing algorith scale ATM witching system in next time.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.264-265
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• 2008

While the reliability of bulk insulation has become important particularly in multilayer boards and embedded boards, electronics are to be used under various environments such as at high temperature and in high humidity. We observed internal space charge behavior for two types of epoxy composites under dc electric fields to investigate the influence of water at high temperature. In the case of glass/epoxy specimen, homocharge is observed at water-treated specimen, and spatial oscillations become clearer in the water-treated specimens. Electric field in the vicinity of the electrodes shows the injection of homocharge. In aramid/epoxy specimens, heterocharge is observed at water-treated specimens, i.e. negative charge accumulates near the anode, while positive charge accumulates near the cathode. Electric field is enhanced just before each electrode. In order to further examine the mechanism of space charge formation, we have developed a new system that allows in situ space charge observation during ion migration tests at high temperature and high humidity. Using this in situ system.

• 전자공학회논문지S
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• 제35S권4호
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• pp.20-29
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• 1998

In this paper, we find the values of near-end crosstalk coefficients in dual-offset stripline of a FR-4 multilayer PCB by an analytic method and a HSPICE simulation method, define calculation errors inananlytic method and the application range, simulate near-end crosstalk coefficients of the FCT(Fast CMOS TTL) in complicated dual-offset stripline by HSPICE and analyze near-end crosstalk and far-end crosstalk coefficients in dual-offset stripline. So, we analyze coupling structure of the near-end crosstalk and far-end crosstalk in the complicated dual-offset striplines that are 1[pF] capacitors termainated, and define a coupling formula of near-end crosstalk and far-end crosstalk coefficients dual-offset striplines.

• 대한전자공학회논문지SD
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• 제48권12호
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• pp.73-81
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• 2011

초고속 디지털 통신시스템의 성능은 빠른 에지율(edge rate), 클럭속도 및 디지털 정보전송방법 등에 영향을 받는다. 특히 고주파 통신시스템의 잡음원은 다수 전송선에서의 신호 간 동시 스위칭, 전원 공급, 신호 반사와 왜곡 등에 의해 발생하며, 다층(multilayer) PCB를 설계할 경우 신호의 충실성이 더욱 훼손된다. 따라서 시스템 H/W의 신호충실성을 얻기 위해 최적 임피던스 정합을 갖는 PCB 설계가 필요하다. 본 논문에서는 시스템 신호의 충실성을 위하여 다층 PCB 선로의 패턴에 따른 트랙계산 이론, 설계에 필요한 임피던스 및 특성 자동 분석 시뮬레이터를 개발한다. 특히 다층으로 PCB를 설계할 때 신호선과 접지부분 배치를 사전에 컴퓨터 모의실험을 통하여 최적조건의 임피던스에 맞는 설계가 가능하도록 시뮬레이터를 개발함은 물론 이를 데이터베이스화한다. 그리하여 제안된 시뮬레이션 툴은 PCB 설계 시 소요되는 시간을 단축하고 경제적인 PCB 개발을 가능케 한다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

• ETRI Journal
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• 제33권3호
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• pp.335-343
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• 2011

The pad pitch of modern radio frequency integrated circuits is in the order of few tens of micrometers. Connecting a large number of high-speed I/Os to the outside world with good signal fidelity at low cost is an extremely challenging task. To cope with this requirement, we need reflection-free transmission lines from an on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow-to-wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept, several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that the impedance variation is less than 3 ${\Omega}$ for a 50 ${\Omega}$ microstrip and S11 better than -9 dB for the frequency range 1 GHz to 6 GHz when the width changes from 165 ${\mu}m$ to 940 ${\mu}m$, and substrate thickness changes from 100 ${\mu}m$ to 500 ${\mu}m$.

• ETRI Journal
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• 제32권2호
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• pp.265-272
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• 2010

To supply a power distribution network with stable power in a high-speed mixed mode system, simultaneous switching noise caused at the multilayer PCB and package structures needs to be sufficiently suppressed. The uni-planar compact electromagnetic bandgap (UC-EBG) structure is well known as a promising solution to suppress the power noise and isolate noise-sensitive analog/RF circuits from a noisy digital circuit. However, a typical UC-EBG structure has several severe problems, such as a limitation in the stop band's lower cutoff frequency and signal quality degradation. To make up for the defects of a conventional EBG structure, a partially located EBG structure with decoupling capacitors is proposed in this paper as a means of both suppressing the power noise propagation and minimizing the effects of the perforated reference plane on the signal quality. The proposed structure is validated and investigated through simulation and measurement in both frequency and time domains.

• ETRI Journal
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• 제41권6호
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• pp.811-819
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• 2019

We propose a substrate with high thermal conductivity, manufactured by the low-temperature co-fired ceramic (LTCC) multilayer circuit process technology, as a new DC/DC converter platform for power electronics applications. We compare the reliability and power conversion efficiency of a converter using the LTCC substrate with the one using a conventional printed circuit board (PCB) substrate, to demonstrate the superior characteristics of the LTCC substrates. The power conversion efficiencies of the LTCC- and PCB-based synchronous buck converters are 95.5% and 94.5%, respectively, while those of nonsynchronous buck converters are 92.5% and 91.3%, respectively, at an output power of 100 W. To verify the reliability of the LTCC-based converter, two types of tests were conducted. Storage temperature tests were conducted at -20 ℃ and 85 ℃ for 100 h each. The variation in efficiency after the tests was less than 0.3%. A working temperature test was conducted for 60 min, and the temperature of the converter was saturated at 58.2 ℃ without a decrease in efficiency. These results demonstrate the applicability of LTCC as a substrate for power conversion systems.