• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.100-103
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• 2008

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.112-115
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• 2008

In this paper, we propose H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18um process including SRAM memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2647-2654
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• 2009

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800K gate counts using Charterd 0.18 um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.2
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• pp.133-139
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• 2017

Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

• The Journal of the Korea Contents Association
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• v.10 no.8
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• pp.59-65
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• 2010

This paper proposes an implementation of a hardware module for transmitting MPEG-2 TS data over the internet protocol (IP)-based network. This implementation consists of two modules; one is an encapsulation module which bridges between n TS packets, where $1\;{\leq}\;n\;{\leq}\;7$, and an IP packets, the other is a packet conversion module which extracts an DSM-CC PS packet from consecutive TS packets and then reconstructing an IP packet. So, these IP packets are carried over 150 megabits per second. Although overall work flow of the proposed DeMUX is based on the reference design of ALTERA, the DeMUX is enhanced by modifying it and performs more functions by adding a packet conversion module. The DeMUX is described by Verilog-HDL (hardware description language) and shows the faithful functionality and throughput through the simulation.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.415-417
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• 2002

운영체제가 지원되지 않는 소규모 기기에서 IPv6의 보안기능을 고성능으로 제공하기 위해본 연구실에서는 IPv6용 IPsec 프로토콜과 암호화 알고리즘을 하드웨어로 구현하였다. 이러한 IPv6용 하드웨어 IPsec을 기반으로 한 보안 서비스를 제공하기 위해서는 안전한 키의 교환과 인증이 중요하다. 이를 위하여 본 논문에서는 IPv6용 하드웨어 IPsec을 위한 키 교환시스템으로서 IKE Module을 설계하여 드라이버 프로그램으로 구현하였다. 그리고 구현된 IKE Module을 IPv6용 하드웨어 IPsec의 드라이버로 탑재하여 기존의 소프트웨어 IKE Module과의 테스트를 통하여 기능을 검증하였다.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.83-86
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• Journal of Power Electronics
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• v.6 no.2
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• pp.114-120
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• 2006

This paper compares two types of direct torque controllers for permanent magnet synchronous motors(PMSMs). These controllers both use a single-chip FPGA(Field Programmable Gate Array) but have differing hardware configurations. One of the controllers was constructed by programming a soft-core CPU and hardware logic circuits written in VHDL(Very high speed IC Hardware Description Language), while the other was constructed of only hardware logic circuits. The characteristics of these two controllers were compared in this paper. The results show the controller constructed of only hardware logic circuits was able to shorten the control period and it was able to suppress the low torque ripple.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.491-492
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• 2008

According to high-speed large scale integration trend of Memory module product, many type of noises, such a reflection, cross-talk simultaneous switching noise, occur on the Package PCB and they make the deterioration of memory module's performance and reliability. As module products have more high efficiency, Hardware of test board and socket has to be considered In test of the high-speed Memory Module. we mainly focused on improvement of Signal integrity Using the High Frequency Test socket that we invented

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.1090-1095
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• 1992

This paper describes the systematic control method of process information transfer and machine cell control in FMS implementation. We have constructed an experimental FMS computer network and control system. The system hardware consists of host computer to manage process data and information transfer of machine cells, cell control computers to control machine cells(NC lathe, machining center). On the other hand, software is made up of oredr management module, NC program searching and generation module, NC part program error check module and cell control module. In this study, we could arrive at conclusion as following : The first, each task could be accomplihed by the efficient information transfer in hierachical computer network. The second, data base system of part programs and process control data is needed for the efficint information transfer and production management. Lastly, expansion of FMS control system could be achieved by the hierachical and decentralized computer control system.