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Implementation of DEMUX Constructing IP Packet from MPEG-2 TS

MPEG-2 TS로부터 IP 패킷을 구성하는 역다중화기 구현

  • 이형 (대전보건대학 방송제작과)
  • Received : 2010.06.08
  • Accepted : 2010.07.27
  • Published : 2010.08.28

Abstract

This paper proposes an implementation of a hardware module for transmitting MPEG-2 TS data over the internet protocol (IP)-based network. This implementation consists of two modules; one is an encapsulation module which bridges between n TS packets, where $1\;{\leq}\;n\;{\leq}\;7$, and an IP packets, the other is a packet conversion module which extracts an DSM-CC PS packet from consecutive TS packets and then reconstructing an IP packet. So, these IP packets are carried over 150 megabits per second. Although overall work flow of the proposed DeMUX is based on the reference design of ALTERA, the DeMUX is enhanced by modifying it and performs more functions by adding a packet conversion module. The DeMUX is described by Verilog-HDL (hardware description language) and shows the faithful functionality and throughput through the simulation.

본 논문은 MPEG-2 Transport Stream (TS) 데이터를 인터넷 망에 전송하기 위한 하드웨어 설계를 제안한다. 제안한 설계는 1개에서 7개 내의 비디오/오디오 스트림을 IP 패킷으로 변환하는 캡슐화 모듈과 연속적인 여러 개의 TS 패킷들로부터 DSM-CC PS 패킷을 추출하여 재구성한 후 IP 패킷으로 변환하는 패킷변환 모듈로 구성된다. 그래서 출력되는 IP 패킷들을 150Mbps 이상의 처리속도를 지원한다. 제안된 모듈들은 ALTERA사의 참조디자인을 토대로 수정 보완한 후 패킷변환 모듈을 추가한 것으로써 하드웨어 기술언어인 Verilog-HDL로 설계하였으며 모의실험을 통해 기능을 검증하였다.

Keywords

References

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