• Title/Summary/Keyword: Graph Interconnection

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Optimal Broadcasting in Recursive circulants under Multi-port Communication (다중포트 통신에서의 재귀원형군에 대한 최적 방송)

  • Choi, Jung;Lee, Hyeong-Ok;Lim, Hyeong-Seok
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.471-474
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    • 1998
  • In this paper, we consider the problem of optimal broadcasting in recursive circulants under multi-port communication model. Recursive circulant G(N, d) that is defined to be a circulant graph with N vertices and jumps of powers of d is a useful interconnection network from the viewpoint of network metrices. Our model assumes that a processor can transmit a message to $\alpha$ neighboring processors simultaneously where $\alpha$ is two or three. For the broadcasting problem, we introduce 3-trees and 4-trees. And then we show that 3-trees and 4-trees are minimum broadcast trees in 2-port model and 3-port model. Using the above results, we show that recursive circulants g(2m, 2) have optimum broadcasting time in 2-port model and 3-port model.

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Implementation of systolic array for 2-D IIR digital filters (2-D IIR digital filter에 대한 systolic array구현)

  • 김수현
    • Proceedings of the Acoustical Society of Korea Conference
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    • 1992.06a
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    • pp.29-32
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    • 1992
  • In this paper, a systolic array structure is derived from the realization of 2-D IIR digital filters directed from the SFG(signal flow graph). After realized the 1-D formed partial systolic array, we implemented the complete systolic array to be cascaded 1-D form. The cascading of partial systolic arrays reduce the storage element which sued to delay input signal. 1-D systolic array is derived from that DG is designed through local communication approach and then it mapping to SFG. The derived structure is very simple and has high throughput because during new imput sample is supplied, new output is obtained every sampling period. And broadcast input signal is eliminated. Since the systolic array has property of regularity, modularity, local interconnection and highly synchronized multiprocessing, thus is very suitable for VLSI implementation.

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One-to-All Broadcasting in Petersen-Torus Networks for SLA and MLA Models

  • Seo, Jung-Hyun;Lee, Hyeong-Ok
    • ETRI Journal
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    • v.31 no.3
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    • pp.327-329
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    • 2009
  • In a network, broadcasting is the dissemination of a message from a source node holding a message to all the remaining nodes through a call. This letter proposes a one-to-all broadcasting algorithm in the Petersen-torus network PT(n, n) for the single-link-available and multiple-link-available models. A PT(n, n) is a regular network whose degree is 4 and number of nodes is $10n^2$, where the Petersen graph is set as a basic module, and the basic module is connected in the form of a torus. A broadcasting algorithm is developed using a divide-and-conquer technique, and the time complexity of the proposed algorithm approximates n+4, the diameter of PT(n, n), which is the lower bound of the time complexity of broadcasting.

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Postorder Fibonacci Circulants (후위순회 피보나치 원형군)

  • Kim, Yong-Seok;Roo, Myung-Gi
    • The KIPS Transactions:PartA
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    • v.15A no.1
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    • pp.27-34
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    • 2008
  • In this paper, We propose a new parallel computer topology, called the Postorder Fibonacci Circulants and analyze its properties. It is compared with Fibonacci cubes, when its number of nodes is kept the same of comparable one. Its diameter is improved from n-2 to $[\frac{n}{3}]$ and its topology is changed from asymmetric to symmetric. It includes Fibonacci cube as a spanning graph.

Design of a Pipelined Datapath Synthesis System for Digital Signal Processing (디지털 신호처리를 위한 파이프라인 데이터패스 합성 시스템의 설계)

  • 전홍신;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.6
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    • pp.49-57
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    • 1993
  • In the paper, we describe the design of a pipelined datapath synthesis system for DSP applications. Taking SFG (Signal Flow Graph) in schematic as inputs, the system generates pipelined datapaths automatically through scheduling and module allocation processes. For efficient hardware synthesis, scheduling and module allocation algorithms are proposed. The proposed scheduling algorithm is of iterative/constructive nature, where the measure of equi-distribution of operations to partitions is adopted as the objective function. Module allocation is performed to reduce the interconnection cost from the initial allocation. In the experiment, we compare the results with those of other systems and show the effectiveness of the proposed algorithms.

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A New Embedding of Pyramids into Regular 2-Dimensional Meshes (피라미드의 정방형 2-차원 메쉬로의 새로운 임베딩)

  • 장정환
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.2
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    • pp.257-263
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    • 2002
  • A graph embedding problem has been studied for applications of resource allocation and mapping the underlying data structure of a parallel algorithm into the interconnection architecture of massively parallel processing systems. In this paper, we consider the embedding problem of the pyramid into the regular 2-dimensional mesh interconnection network topology. We propose a new embedding function which can embed the pyramid of height N into 2$^{N}$ x2$^{N}$ 2-dimensional mesh with dilation max{2$^{N1}$-2. [3.2$^{N4}$+1)/2, 2$^{N3}$+2. [3.2$^{N4}$+1)/2]}. This means an improvement in the dilation measure from 2$^{N}$ $^1$in the previous result into about (5/8) . 2$^{N1}$ under the same condition.condition.

A Topology Independent Heuristic Load Balancing Algorithm for Multiprocessor Environment (다중 프로세서 환경에서 연결구조에 무관한 휴리스틱 부하평형 알고리즘)

  • Song Eui-Seok;Sung Yeong-Rak;Oh Ha-Ryoung
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.42 no.1
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    • pp.35-44
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    • 2005
  • This paper proposes an efficient heuristic load balancing algorithm for multiprocessor systems. The algorithm minimizes the number of idle links to distribute load traffic and reduces its communication cost. Each processor iteratively tries to transfer unit load to/from all neighbor processors. However, real load transfer is collectively done after all load traffic is calculated. This prevents useless traffic and thus reduces the overall load traffic. The proposed algorithm can be employed in various interconnection topologies with slight modifications. In this paper, it is applied to hypercube, mesh, k-ary n-cube and general graph environments. For performance evaluation, simulation studies are performed. The proposed algorithm and the well-known existing algorithms are implemented and compared. The results show that the proposed algorithm always balances the loads perfectly. furthermore, in comparison with the existing algorithms, it reduces the communication costs by 77%, 74% and 73% in the hypercube, the mesh, and k-ary n-cube, respectively.

V-SUPER VERTEX OUT-MAGIC TOTAL LABELINGS OF DIGRAPHS

  • Devi, Guruvaiah Durga;Durga, Morekondan Subhash Raja;Marimuthu, Gurusamy Thevar
    • Communications of the Korean Mathematical Society
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    • v.32 no.2
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    • pp.435-445
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    • 2017
  • Let D be a directed graph with p vertices and q arcs. A vertex out-magic total labeling is a bijection f from $V(D){\cup}A(D){\rightarrow}\{1,2,{\ldots},p+q\}$ with the property that for every $v{\in}V(D)$, $f(v)+\sum_{u{\in}O(v)}f((v,u))=k$, for some constant k. Such a labeling is called a V-super vertex out-magic total labeling (V-SVOMT labeling) if $f(V(D))=\{1,2,3,{\ldots},p\}$. A digraph D is called a V-super vertex out-magic total digraph (V-SVOMT digraph) if D admits a V-SVOMT labeling. In this paper, we provide a method to find the most vital nodes in a network by introducing the above labeling and we study the basic properties of such labelings for digraphs. In particular, we completely solve the problem of finding V-SVOMT labeling of generalized de Bruijn digraphs which are used in the interconnection network topologies.

Design and performance analysis of fault tolerant multistage interconnection network with destination tag algorithm (목적지 태그 라우팅 알고리즘을 사용하는 결함허용 다단계 상호연결망의 설계 및 성능분석)

  • 정종인
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.6
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    • pp.1137-1147
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    • 1997
  • I propose a RZETA network consisted of switching elements(SEs) that have regular links and alternate links. A modified Zeta nework used for the RZETA network's regular links and a MIN used for its alternate links are generated using the graph theory. The RZETA network is driven from merging the formaer and latter MINs. A necessary and sufficient condition for modified Zeta network to be a nonblocking network is also presented. This condition is a ufficient condition for RZETA network with a faulty link or a faulty SE to be nonblocked. Performance of the RZETA network is analyzed by modification of the model of 2-dilated Banyan network and its performance is compared with existing redundant path networks, when packet arrival rate of each source is 1.

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Cycle Embedding of Faulty Recursive Circulants (고장난 재귀원형군의 사이클 임베딩)

  • 박정흠
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.1_2
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    • pp.86-94
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    • 2004
  • In this paper, we show that $ G(2^m, 4), m{\geq}3$with at most m-2 faulty elements has a fault-free cycle of length 1 for every ${\leq}1{\leq}2^m-f_v$ is the number of faulty vertices. To achieve our purpose, we define a graph G to be k-fault hypohamiltonian-connected if for any set F of faulty elements, G- F has a fault-free path joining every pair of fault-free vertices whose length is shorter than a hamiltonian path by one, and then show that$ G(2^m, 4), m{\geq}3$ is m-3-fault hypohamiltonian-connected.