• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 추계학술대회 논문집 학회본부
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• pp.240-242
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• 1994

Spectroscopic ellipsometry(SE) was employed to characterize the Si/$Si_{1-x}Ge_x$ heterostructure. The dielectric function spectrum of $Si_{1-x}Ge_x$ at an arbitrary x value in the spectral range of $1.5{\sim}4.5\;eV$ was computed by EMA (effective medium approximation) model using the available optical constants measured at a number of fixed x values of Ge composition. The thickness and the Ge composition of $Si_{1-x}Ge_x$ measured by SE was compared with those measured by RBS. DC bias effect on the $E_2$ peak of dielectric function spectra was studied.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.24.2-24.2
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• 2009

Nanostuctures such as nanodot and nanowire have been extensively studied as building blocks for nanoscale devices. However, the direct growth of the nanostuctures at the desired position is one of the most important requirements for realization of the practical devices with high integrity. Self-assembled nanotemplate is one of viable methods to produce highly-ordered nanostructures because it exhibits the highly ordered nanometer-sized pattern without resorting to lithography techniques. And selective epitaxial growth (SEG) can be a proper method for nanostructure fabrication because selective growth on the patterned openings obtained from nanotemplate can be a proper direction to achieve high level of control and reproducibility of nanostructucture fabrication. Especially, SiGe has led to the development of semiconductor devices in which the band structure is varied by the composition and strain distribution, and nanostructures of SiGe has represented new class of devices such nanowire metal-oxide-semiconductor field-effect transistors and photovoltaics. So, in this study, various shaped SiGe nanostructures were selectively grown on Si substrate through ultrahigh vacuum chemical vapor deposition (UHV-CVD) of SiGe on the hexagonally arranged Si openings obtained using nanotemplates. We adopted two types of nanotemplates in this study; anodic aluminum oxide (AAO) and diblock copolymer of PS-b-PMMA. Well ordered and various shaped nanostructure of SiGe, nanodots and nanowire, were fabricated on Si openings by combining SEG of SiGe to self-assembled nanotemplates. Nanostructure fabrication method adopted in this study will open up the easy way to produce the integrated nanoelectronic device arrays using the well ordered nano-building blocks obtained from the combination of SEG and self-assembled nanotemplates.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.314-316
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• 1997

We have studied the epitaxial growth and electrical properties of $Si_{0.8}Ge_{0.2}$, films on Si substrates at $550^{\circ}C$ by LPCVD. In a low $PH_3$, partial pressure region such as below 1.25 mPa, the phosphorus doping concentration increased proportionally with increasing $PH_3$ partial pressure while the deposition rate and the Ge fraction x were constant. In a higher $PH_3$ partial pressure region, the phosphorus doping concentration and the deposition rate decreased, while the Ge fraction slightly increased. The dependence of P incorporation rate on the $PH_3$ partial pressure was similar to the phosphorus doping concentration. According to test results, it suggests that high surface coverage of phosphorus atoms suppress both the $SiH_4$ adsorption/reaction and the $GeH_4$ adsorption/reaction on the surfaces, and the effect is more stronger on $SiH_4$ than on $GeH_4$. In a higher $PH_3$ partial pressure region, the deposition is largely controlled by surface coverage effect of phosphorus atoms.

• ETRI Journal
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• 제41권6호
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• pp.829-837
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• 2019

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computer-aided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology.

• 대한전자공학회논문지SD
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• 제48권5호
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• pp.12-17
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• 2011

본 연구에서는 $Si_xGe_{1-x}$ 버퍼층 위에 성장된 strained-Si에 Ge 농도에 따라 n-MOSFET를 제작하고 소자 제작 후의 열처리 온도에 따른 소자의 아날로그 성능을 측정 분석하였다. 전자의 유효 이동도는 Ge 농도가 증가함에 따라 증가하였으나 32%로 높을 때에는 열처리 온도에 상관없이 오히려 감소하는 것으로 측정되었다. 상온에서 Ge 농도가 증가함에 따라 증가 소자의 아날로그 성능 지수가 우수하였으나 32% 농도에서는 오히려 좋지 않았다. 고온에서 strained-Si의 전자 유효이동도 저하가 Si보다 심하기 때문 SGOI 소자의 아날로그 성능 저하가 SOI 소자보다 심한 것을 알 수 있었다.

• ETRI Journal
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• 제25권3호
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• pp.203-209
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• 2003

This paper reports on our investigation of DC and RF characteristics of p-channel metal oxide semiconductor field effect transistors (pMOSFETs) with a compressively strained $Si_{0.8}Ge_{0.2}$ channel. Because of enhanced hole mobility in the $Si_{0.8}Ge_{0.2}$ buried layer, the $Si_{0.8}Ge_{0.2}$ pMOSFET showed improved DC and RF characteristics. We demonstrate that the 1/f noise in the $Si_{0.8}Ge_{0.2}$ pMOSFET was much lower than that in the all-Si counterpart, regardless of gate-oxide degradation by electrical stress. These results suggest that the $Si_{0.8}Ge_{0.2}$ pMOSFET is suitable for RF applications that require high speed and low 1/f noise.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.453-456
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• 1998

The electrical properties of $Si_{1-x}Ge_{x}$ samples have been investigated. The sample structures were grown by MBE (molecular geam epitaxy) with Ge mole-fraction of x=0.0, x=0.05, x=0.1, and x=0.2. To examine the influence of the thermal processing, the $O_{2}$ and N$_{2}$ process were performed at 800[.deg. C] and 900[.deg. C], respectively. After this thermal process, hall measurements have been done over a wide range of the ambient temperature between 320[.deg. K] and 10[.deg. K] to find the temperature dependence using the comparessed-He gas system. The Ge-rich layer has been formed at the $SiO_{2}$/SiGe interface and it has an effect on the hall mobility. And it has been found that hall mobility was increased by the $N_{2}$ annealing process comparing with dry oxidation process at both 800[.deg.C] and900[.deg. C].

• 한국전기전자재료학회논문지
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• 제18권4호
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• pp.285-296
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• 2005

Reduced pressure chemical vapor deposition technology has been used to study SiGe heterostructure epitaxy and device issues, including SiGe relaxed buffers, proper control of Ge component and crystalline defects, two dimensional delta doping, and their influence on electrical properties of devices. From experiments, 2D profiles of B and P presented FWHM of 5 nm and 20 nm, respectively, and doses in 5×10/sup 11/ ∼ 3×10/sup 14/ ㎝/sup -2/ range. The results could be employed to fabricate SiGe/Si heterostructure field effect transistors with both Schottky contact and MOS structure for gate electrodes. I-V characteristics of 2D P-doped HFETs revealed normal behavior except the detrimental effect of crystalline defects created at SiGe/Si interfaces due to stress relaxation. On the contrary, sharp B-doping technology resulted in significant improvement in DC performance by 20-30 ％ in transconductance and short channel effect of SiGe HMOS. High peak concentration and mobility in 2D-doped SiGe heterostructures accompanied by remarkable improvements of electrical property illustrate feasible use for nano-sale FETs and integrated circuits for radio frequency wireless communication in particular.

• 한국광학회지
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• 제13권3호
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• pp.215-222
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• 2002

광기록매체용 Ge-Sb-Te다층박막 성장과정을 in-situ 타원계를 사용하여 실시간으로 모니터하여 각 층의 두께를 제어하고 성장된 Ge-Sb-Te 다층박막을 ex-site 분광타원법으로 확인하였다. 보호층인 ZnS-SiO$_2$와 기록층인 Ge$_2$Sb$_2$Te$_{5}$을 단결정실리콘 기층 위에 스퍼터링 방법으로 각각 성장시키면서 구한 타원상수 성장곡선을 분석하여 성장에 따르는 보호층의 균일성 및 기록 층의 밀도변화를 파악하고 이를 기초로 하여 Ge-Sb-Te광기록 다층박막의 두께를 정밀하게 제어하였다. Ge$_2$Sb$_2$Te$_{5}$ 단층박막 시료의 복소굴절율은 eX-Situ 분광타원분석을 통하여 구하였다. 제작된 다층구조는 설정된 다층구조인 ZnS-SiO$_2$(1400$\AA$)$\mid$ GST(200 $\AA$)$\mid$ZnS-SiO$_2$(200$\AA$)와 각 층의 두께 및 전체 두께에서 1.5% 이내에서 일치하는 정확도를 보여주었다.주었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.