• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.12-17
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• 2011

In this work, the analog performances of n-MOSFET fabricated on strained-Si/relaxed Si buffer layer with Ge mole fractions and thermal annealing temperatures after device fabrication have been characterized in Depth. The effective electron mobility was increased with the increase of Ge mole fraction for all annealing temperatures. However the effective electron mobility was decreased at the Ge mole fraction of 32%. The analog performances were enhanced with the increase of Ge mole fraction at the room temperature but they were degraded at the Ge mole fraction of 32%. Since the degradation of the effective electron mobility of strained-Si layer is more significant than one of conventional Si layer at elevated temperature, the degradation of analog performances of SGOI devices were increased than those of SOI devices.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.415-419
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• 2014

나노스케일 MOSFET에서 leakage current는 중요한 이슈로서 $Si_{1-x}Ge_x$ alloy를 substrate로 사용할 경우 leakage current에 어떤 영향을 미칠 것인지 시뮬레이션을 통하여 알아보았다. $Si_{1-x}Ge_x$ alloy에서 Ge의 비율이 증가할수록 유효질량이 작아졌으나 conduction band minimum의 위치는 Si에 비해 상승하였다. 이로 인해 tunneling 확률이 증가하여 $Si_{1-x}Ge_x$ alloy를 substrate로 사용할 경우 leakage current를 더욱 증가시키게 되었다.

• ETRI Journal
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• v.27 no.4
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.6
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• pp.491-495
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• 2007

This paper has demonstrated the electrical properties of SiGe pMOSFETs fabricated on both bulk-Si and PD SOI substrates. Two principal merits, the mobility increase in strained-SiGe channel and the parasitic capacitance reduction of SOI isolation, resulted in improvements in device performance. It was observed that the SiGe PD SOI could alleviate the floating body effect, and consequently DIBL was as low as 10 mV/V. The cut-off frequency of device fabricated on PD SOI substrate was roughly doubled in comparison with SiGe bulk: from 6.7 GHz to 11.3 GHz. These experimental result suggests that the SiGe PD SOI pMOSFET is a promising option to drive CMOS to enhance performance with its increased operation frequency for high speed and low noise applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.9-18
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• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.1
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• pp.1-6
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• 2006

High performance $Si_{0.8}Ge_{0.2}$ heterostructure metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated using well-controlled delta-doping of boron and $Si_{0.8}Ge_{0.2}$/Si heterostructure epitaxal layers grown by reduced pressure chemical vapor deposition. In this paper, we report 1/f noise characteristics of the SiGe pMOSFETs measured under various bias conditions of the gate and drain voltages changing in linear operation regions. From the noise spectral density, we found that the gate and drain voltage dependence of the noise represented same features, as usually scaled with $f^{-1}$ However, 1/f noise was found to be much lower in the device with boron delta-doped layer, by a factor of $10^{-1}_10^{-2}$ in comparison with the device fabricated without delta-doped layer. 1/f noise property of delta-doped device looks important because the device may replace bipolar transistors most commonly embedded in high-frequency oscillator circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.5-6
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• 2005

High performance SiGe heterostructure metal-oxide-semiconductor field effect transistors(MOSFETs) were fabricated using well-controlled delta-doping of boron and SiGe/Si heterostructure epitaxal layers grown by reduced pressure chemical vapor deposition. In this paper, we report 1/f noise characteristics of the SiGe MOSFETs measured under various bias conditions of the gate and drain voltages changing in linear operation regions. From the noise spectral density, we found that the gate and drain voltage dependence of the noise represented same features, as usually scaled with $f^1$. However, 1/f noise was found to be much lower in the device with boron delta-doped layer, by a factor of $10^{-1}\sim10^{-2}$ in comparion with the device fabricated without delta-doped layer. 1/f noise property of delta-doped device looks important because the device may replace bipolar transistors most commonly embedded in high-frequency oscillator circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.150-151
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• 2006

$Si_{0.88}Ge_{0.12}$/Si heterostructure channels grown by RPCVD were employed to n-type metal oxide semiconductor field effect transistors(MOSFETs), and their electrical properties were investigated. SiGe nMOSFETs presented very high transconductance compared to conventional Si-bulk MOSFETs, regardless substantial drawbacks remaining in subthreshold-slope, $I_{off}$, and leakage current level. It looks worthwhile to utilize excellent transconductance properties into rf applications requesting high speed and amplification capability, although optimization works on both device structure and unit processes are necessary for enhanced isolation and reduced power dissipation.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.143.1-143.1
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• 2016

Ge is a promising candidate to replace Si in MOSFET because of its superior carrier mobility, particular that of the hole. However Ge oxide is thermodynamically unstable. At elevated temperature, GeO is formed at the interface of Ge and GeO2, and its formation increases the interface defect density, degrading its device performance. In search for a method to surmount the problem, we investigated Ge oxidation through an inert capped oxide layer. For this work, we prepared low doped n-type Ge(100) wafer by removing native oxide and depositing a capping layer, and show that GeO2 interface can be successfully grown through the capping layer by thermal oxidation in a furnace. The thickness and quality of thus grown GeO2 interface was examined by ellipsometry, XPS, and AFM, along with I-V and C-V measurements performed at 100K to 300K. We will present the result of our investigation, and provide the discussion on the oxide growth rate, interface state density and electrical characteristics in comparison with other studies using the direct oxidation method.