• Journal of Korea Water Resources Association
• /
• v.37 no.7
• /
• pp.541-552
• /
• 2004

In this paper, ascending functions of the pool-and-weir fishway which has been established for the upstream migration of migratory fish at Jamsil Weir in the lower part of the Han River was assessed by applying tile Existing Fishway Measurement Method, and measures to improve these functions were suggested. The primary fish which ascended the fishway during the period of measurement was Erythroculter erythropterus Basilewsky, greater than 29cm in the body length. A total of 361 individual fish were collected with traps established at the exit of the fishway The maximum ascending capacity for the fish was 2.53${\times}$10^{-3}$ fish/hr/g. The fishway of Jamsil Weir does not satisfy the various fish species inhabiting in the river. Especially, small fishes of lower swimming ability may not ascend the fishway because the difference in water levels between upper and lower pools in the fishway was too large at the exit and there was too much discharge flowing into the fishway. This fishway does not have a roll in the ascending function for other species except Erythroculter erythropterus Basilewsky and Hemibarbus labeo Pallas, for which swimming ability is great. In order to improve the ascending function of the fishway, the structures of the fishway need to be changed so that various species in the river can easily ascend and the fishway function be taken into consideration in operation of the gates of the weir. Additional construction of fishways on both sides of the lower flow channel are needed to correct a decline in the fishway effectiveness due to continuous flow over the fixed part of the weir.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.8
• /
• pp.2484-2496
• /
• 2000

High speed switches have been developing to interconnect a large number of nodes. It is important to analyze the switch performance under various conditions to satisfy the requirements. Queueing analysis, in general, has the intrinsic problem of large state space dimension and complex computation. In fact, The petri net is a graphical and mathematical model. It is suitable for various applications, in particular, manufacturing systems. It can deal with parallelism, concurrence, deadlock avoidance, and asynchronism. Currently it has been applied to the performance of computer networks and protocol verifications. This paper presents a framework for modeling and analyzing ATM switch using stochastic activity networks (SANs). In this paper, we provide the ATM switch model using SANs to extend easily and an approximate analysis method to apply A TM switch models, which significantly reduce the complexity of the model solution. Cell arrival process in output-buffered Queueing A TM switch with finite buffer is modeled as Markov Modulated Poisson Process (MMPP), which is able to accurately represent real traffic and capture the characteristics of bursty traffic. We analyze the performance of the switch in terms of cell-loss ratio (CLR), mean Queue length and mean delay time. We show that the SAN model is very useful in A TM switch model in that the gates have the capability of implementing of scheduling algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.11
• /
• pp.8-15
• /
• 2009

Side-channel attacks including the differential power analysis attack are often more powerful than classical cryptanalysis and have to be seriously considered by cryptographic algorithm's implementers. Various countermeasures have been proposed against such attacks. In this paper, we deal with the masking method, which is known to be a very effective countermeasure against the differential power analysis attack and propose new gate-level conversion methods between Boolean and arithmetic masks. The new methods require only 6n-5 XOR and 2n-2 AND gates with 3n-2 gate delay for converting n-bit masks. The basic idea of the proposed methods is that the carry and the sum bits in the ripple adder are manipulated in a way that the adversary cannot detect the relation between these bits and the original raw data. Since the proposed methods use only bitwise operations, they are especially useful for DPA-securely implementing cryptographic algorithms in hardware which use both Boolean and arithmetic operations. For example, we applied them to securely implement the block encryption algorithm SEED in hardware and present its detailed implementation result.

• Design & Manufacturing
• /
• v.14 no.1
• /
• pp.1-7
• /
• 2020

In this study, the variation of the shrinkage in the thickness direction of the molded parts according to the gate size of the polymer core fabricated through the 3D printer using the SLS method was studied. The polymer cores are laser sintered and the powder material is nylon base PA2200. The polymer cores have lower heat transfer rate and rigidity than the metal core due to the characteristics of the material. Therefore, the injection molding test conditions are set to minimize the deformation of the core during the injection process. The resin used in the injection molding test is a PP material. The packing condition was set to 80, 90 and 100% of the maximum injection pressure for each gate size. The runner diameter used was ∅3mm, and the gates were fabricated in semicircle shapes with cross sections 1, 2, and 3 ㎟, respectively. Thickness measurement was performed for 10 points at 2.5 mm intervals from the point 2.5 mm away from the gate, and the shrinkage to thickness was measured for each point. The shrinkage rate according to the gate size tends to decrease as the cross-sectional area decreases as the maximum injection pressure increases. The average thickness shrinkage rate was close to 0% when the packing pressure was 90% for the gate area of 1mm2. When the holding pressure was set to 100%, the shrinkage was found to decrease by 3% from the standard dimension due to the over-packing phenomenon. Therefore, the smaller the gate, the more closely the molded dimensions can be molded due to the high pressure generation. It was confirmed that precise packing process control is necessary because over-packing phenomenon may occur.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.6
• /
• pp.431-441
• /
• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.12
• /
• pp.99-108
• /
• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise

• Journal of Korea Water Resources Association
• /
• v.37 no.8
• /
• pp.653-662
• /
• 2004

In this study, the method of Increasing the flood control as well as conservation effects is studied by joint operation of Hwacheon and Peace Dam. After completing the second phase of the construction of the Peace Dam, the dam crest height will be increased from 225m and the storage capacity will also be increased. If storage capacity is increased and gates are installed, it will assist not only flood control but also conservation of the entire Han river basin. Considering the change of conservation levels, the change of the restricted water level of the Hwacheon Dam in flood season, and the inflow change into the Peace Dam through the simulated reservoir operation, the annual average power of Hwacheon Dam with 95% reliability, annual firm power, the volume of water supply is calculated. As a result, when the conservation level of the Peace Dam and the restricted water level of the Hwacheon Dam are increased, the generation capacity will be improved. However, even though the inflow decrease, the generation capacity will not be affected. If the inflow decrease under the same conditions, the water supply capability will be reduced to the range from 35% to 40%. It is necessary to increase conservation level to keep the same water supply capability.

• Journal of architectural history
• /
• v.18 no.5
• /
• pp.59-80
• /
• 2009

The purpose of this study is to investigate the history, space structures, blueprint, and techniques of the construction of Nam-hea city walls. Nam-hea city walls were relocated in 1439 from Whagumhun-Sansung(火金峴山城) to the present site, nearby Nam-hea Um.(南海邑) The city walls were rebuilt after they were demolished during Japanese invasion on Korea in 1592 and their reconstruction was also done in 1757. At present, the city walls only partially remained due to the urbanization of the areas around them. A plane form of the City wall is a square, and the circumference os approximately 1.3km. According to the literature, the circumference of the castle walls is 2,876尺, the height is 13尺, and the width is 13尺 4寸. Hang-Kyo(鄕校). SaGikDan(社稷壇), YoeDan(厲壇), SunSo(船所) which is a harbor, as well as government and public offices such as Kaek-Sa(客舍) and Dong-Hun(東軒) existed inside the castle walls. Inside the castle walls were one well, five springs, one ditch, and one pond, and in the castle walls, four castle gates, three curved castle walls, and 590 battlements existed. The main government offices inside castle walls were composed of Kaek-Sa, Dong-Hun, and Han-Chung(鄕廳) their arrangements were as follows. Kaek-Sa was situated toward North. Dong-Hun was situated in the center of the west castle walls. The main roads were constructed to connect the North and South castle gate, and subsidiary roads were constructed to connect the East and West castle gate. The measurement used in the blueprint for castle wall was Pobaek-scale(布帛尺:1尺=46.66cm), and one side of it was 700尺. South and North gate were constructed in the center of South and North castle wall, and curved castle walls was situated there. One bastion was in the west of curved castle walls and two bastions were in the east of curved castle walls. The east gate was located in the five eighths of in the east castle wall. Two bastions were situated in the north, on bastion in the south, one bastion in the south, and four bastions in the west castle wall. The castle walls were constructed in the following order: construction of castle field, construction of castle foundation, construction of castle wall, and cover the castle foundation. The techniques used in the construction of the castle walls include timber pile(friction pile), replacement method by excavation.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.1
• /
• pp.35-41
• /
• 2000

This paper considers the consturction of 24/25 I-NRZI (Interleaved - Non Return to Zero Inverse) modulator designs for DVCR (Digital Video Cassette Recorder), and size of validity bit in order to store the amplitude value of square-wave and the standard data ( sine and cosine coefficients) at ROM Table that to acceptable the spectrum standard. The validity bit size of the standard data and the amplitude value of square-wave that to store at ROM Table are affected the size of pilot signal on the output spectrum, and the hardware size of modulator. At the designable 24/25 I-NRZI modulator, we simulated using random pattern (F0,F1,F2) that to verification the output data of the spectrum. Moreover, the resultant of the spectrum analysis, at the optimizing value, is 0.065 on the amplitude value of square-wave, and 3bit on the size of bit in order to store the standared data at ROM Table. In order to verify the hardware of designable 24/25 I-NRZI modulator, we perform to modeling of C-language firstly, and coding to Verilog HDL (Cadence Verilog XL) and synthesized using Synopsys (Library "Samsung KG75") tool as a base of spectrum results. In a foundation of this result, we are considered the size of hardware. In this paper, a considerable 24/25 I-NRZI modulator designable less than 10,000 gates as that is improved consturction as regards the path method of pre-coder etc, and able to application digital camcorders as now practical use.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.2A
• /
• pp.177-183
• /
• 2009

In this paper, we propose an improved anti-collision algorithm. We have designed an anti-collision unit using this algorithm for the 18000-6 Type C Class 1 Generation 2 standard (Gen2). The Gen2 standard uses a Q-algorithm for incremental method on the Dynamic Slot-Aloha algorithm. It has basically enhanced performance over the Slot-Aloha algorithm. Unfortunately, there are several non-clarified parts: initial $Q_{fp}$ value, weighted C, and the ending point of the algorithm. If an incorrect value is selected, it causes degradation in performance. Thus we propose an improved anti-collision algorithm by clearly defining the vague parts of the existing algorithm. Simulation results showed an improved performance of up to 34.8% using an optimized value of C and the initial $Q_{fp}$ value. With the ending condition, performance is 34.7%. The anti-collision unit is designed using the Verilog HDL. The module was synthesized using Synopsys' Design Compiler and the TSMC $0.2{\mu}m$ standard cell library. The synthesized result yielded 3,847 gates, and was guaranteed under the proposed working frequency of 19.2MHz.