• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.923-926
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• 2003

This paper presents a novel low voltage reference circuit under the MOS threshold voltage(V$_{th}$) in standard CMOS process. It is based on the weighted difference of the gate-source voltages of an NMOS and a PMOS operating in saturation region. The voltage reference is designed for low power OLED driver ICs. The proposed circuit is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The minimum supply voltage is 2V, and the typical temperature coefficient is 99.6ppm/ C.C.

• 전력전자학회논문지
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• 제4권1호
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• pp.99-104
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• 1999

최근 산업이 대규모화함에 따라 고압 전력 변환 장치의 필요성이 증가하고 있고, 이에 따라 전력용 반도체 소자의 직렬 구동이 많이 이용되고 있다. 소자의 직렬 구동은 소자간에 적절한 전압 분배가 이루어져 개별 소자에 정격이상의 과전압이 인가되는 것을 방지하는 것이 큰 관건이다. 또한 고전압 회로에서는 부유 인덕턴스에 의한 소자의 과전압도 방지하여야 한다. 본 논문에서는 직렬 연결된 IGBT의 턴-오프 과도상태시 컬렉터 전압 기울기 조절로 안정된 전압 분배와 과전압을 방지하는 새로운 게이트 구동기법을 제안한다. 제안하는 게이트 구동기법은 컬렉터 전압을 검출하여 능동적으로 게이트 신호를 제어함으로써 과전압을 제한한다. 새로운 IGBT 게이트 구동회로를 제작하고 직렬 연결된 IGBT 회로에 적용하여 게이트 구동기법의 타당성을 검증하였다.

• 대한전자공학회논문지SD
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• 제37권1호
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• pp.83-91
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• 2000

본 논문은 수 만 개 이상의 소자로 구성된 대규모 배선 회로를 SPICE와 같은 회로 시뮬레이터로 분석할 수 있도록 그 규모를 축소 시키는 새로운 방법을 제안하고 있다. 이 방법은 배선 회로의 구조 분석과 Elmore 시정수에 바탕을 둔 여러 가지 규칙들을 사용하여 회로 소자 개수를 줄여나가는 기존의 방법과 근본적으로 다른 접근 방식이다. AWE 기법을 사용하여 CMOS 게이트 구동 측성 모델을 구하고, 이 모델에 배선 회로를 연결하여 타임 모멘트를 계산한 다음, 이와 동일한 모멘트를 갖는 등가 RC 회로를 합성하는 과정을 거친다. 이 방법을 사용하면 배선 회로를 구동하는 CMOS 게이트의 특성을 높이는 수준의 정확도로 방영할 수 있을 뿐만 아니라, 압축된 회로의 크기가 원래 배선 회로에 포함되어 있던 소자의 개수와 관계없이 출력 노드의 개수에 비례하여 결정되므로, 대규모 배선 회로에 대해서 압축율이 극히 우수하다. 이 방법을 C 프로그램으로 구현하여 0.5${\mu}m$ CMOS ASIC 제품에 적용한 결과, 99% 이상의 극히 우수한 압축율을 보였으며, 원래의 배선 회로 대비 지연 시간 측면에서 1~10%의 오차를 갖는 정확도를 나타내었다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.205-207
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• 2008

The new process for hybrid silicon thin film transistor (TFT) using DPSS laser has been developed for realizing both low-temperature poly-Si (LTPS) TFT and a-Si:H TFT on the same substrate as a backplane of active matrix liquid crystal display. LTPS TFTs are integrated on the peripheral area of the panel for gate driver integrated circuit and a-Si:H TFTs are used as a switching device for pixel in the active area. The technology has been developed based on the current a-Si:H TFT fabrication process without introducing ion-doping and activation process and the field effect mobility of $4{\sim}5\;cm^2/V{\cdot}s$ and $0.5\;cm^2/V{\cdot}s$ for each TFT was obtained. The low power consumption, high reliability, and low photosensitivity are realized compared with amorphous silicon gate driver circuit and are demonstrated on the 14.1 inch WXGA+ ($1440{\times}900$) LCD Panel.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1085-1088
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• 2007

A new DC-DC converter was designed for gate driver circuit using low temperature poly-Si TFT technology. To achieve high efficiency and small area, we proposed a cross-coupled type DC-DC converter which converts 5V of input voltage to 9V of output voltage and supplies 120$\mu$A of current to load. Its efficiency is 92.9% and the area is reduced as much as 19% compared to the previously reported latch type DC-DC converter.

• Journal of Power Electronics
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• 제16권1호
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• pp.362-373
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• 2016

The on-line measurement of high-power IGBT collector current is important for the hierarchical control and short-circuit and overcurrent protection of its driver and the sensorless control of the converter. The conventional on-line measurement methods for IGBT collector current are not suitable for engineering measurement due to their large-size, high-cost, low-efficiency sensors, current transformers or dividers, etc. Based on the gate driver, this paper has proposed a current measuring circuit for IGBT collector current. The circuit is used to conduct non-intervention on-line measurement of IGBT collector current by detecting the voltage drop of the IGBT power emitter and the auxiliary emitter terminals. A theoretical analysis verifies the feasibility of this circuit. The circuit adopts an operational amplifier for impedance isolation to prevent the measuring circuit from affecting the dynamic performance of the IGBT. Due to using the scheme for integration first and amplification afterwards, the difficult problem of achieving high accuracy in the transient-state and on-state measurement of the voltage between the terminals of IGBT power emitter and the auxiliary emitter (u_Ee) has been solved. This is impossible for a conventional detector. On this basis, the adoption of a two-stage operational amplifier can better meet the requirements of high bandwidth measurement under the conditions of a small signal with a large gain. Finally, various experiments have been carried out under the conditions of several typical loads (resistance-inductance load, resistance load and inductance load), different IGBT junction temperatures, soft short-circuits and hard short-circuits for the on-line measurement of IGBT collector current. This is aided by the capacitor voltage which is the integration result of the voltage uEe. The results show that the proposed method of measuring IGBT collector current is feasible and effective.

• Journal of Power Electronics
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• 제14권2호
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• pp.292-301
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• 2014

This paper presents a new configuration for a three-phase multilevel voltage source inverter. The main bridge is built from a classical three-phase two-level inverter and three bidirectional switches. A variable DC-link employing two unequal DC voltage supplies and four switches is connected to the main circuit in such a way that the proposed inverter produces four levels in the output voltage waveform. In order to obtain the desired switching gate signals, the fundamental frequency staircase modulation technique is successfully implemented. Furthermore, the proposed structure is extended and compared with other types of multilevel inverter topologies. The comparison shows that the proposed inverter requires a smaller number of power components. For a given number of voltage steps N, the proposed inverter requires N/2 DC voltage supplies and N+12 switches connected with N+7 gate driver circuits, while diode clamped or flying capacitor inverters require N-1 DC voltage supplies and 6(N-1) switches connected with 6(N-1) gate driver circuits. A prototype of the introduced configuration has been manufactured and the obtained simulation and experimental results ensure the feasibility of the proposed topology and the validity of the implemented modulation technique.

• ETRI Journal
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• 제26권1호
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• pp.7-13
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• 2004

To improve the characteristics of breakdown voltage and specific on-resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon-on-insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on-resistance. The breakdown voltage and the specific on-resistance of the fabricated device is 352 V and $18.8 m{\Omega}{\cdot}cm^2$ with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on-state is over 200 V and the saturation current at $V_{gs}=5V$ and $V_{ds}$=20V is 16 mA with a gate width of $150{\mu}m$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• 대한전자공학회논문지SD
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• 제46권3호
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• pp.96-102
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• 2009

본 논문에서는 600V/200A 또는 1200V/150A와 같은 고전력 절연 게이트 소자를 구동 및 보호하기 위한 파워 IC에 대한 연구에 대해서 살펴보았다. 고전력 소자의 구동을 위해서 최대 Sourcing 전류 4A, 최대 Sinking 전류 8A로 설계하였으며, 과전류 보호회로로는 전력소자의 드레인(콜렉터) 전압을 측정하여, Desaturation을 검출하는 방식을 사용하였다. 또한 과전류 보호시 기생 인덕턴스에 의해 발생할 수 있는 과전압을 억제하기 위해서 soft-shutdown 기능을 추가하였다. 제안된 게이트 구동 IC는 동부하이텍의 고전압 BCDMOS 공정인 0.35um BDA350 공정과 PDK를 사용하여 설계 및 제작하여 검증하였다.