• Journal of Korean Society for Quality Management
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• v.42 no.3
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• pp.279-290
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• 2014

Purpose: The purpose of this study is to propose adoption of QFD and Stage-gate in order to analyze the quality of korea defense system. Methods: Drawing change data of initial production phase in korea defense system were anlayzed and a practical method was proposed. Results: The results of this study are as follows; Off line Quality Control should be introduced in development phase. Specially, in case of defense system, the best method is QFD(Quality Function Deployment) and Stage-gate process. At first, QFD 1 step defines product planning from VOC(Voice Of Customer), QFD 2 step specifies part planning from product planning, QFD 3 step defines process planning from part planning, QFD 4 step defines production planning from previous process planning. Secondly, Stage-gate process is adopted. This study is proposed 5 stage-gate in case of korea defense development. Gate 1 is located after SFR(System Function Review), Gate 2 is located after PDR(Preliminary Design Review), Gate 3 is located after CDR(Critical Design Review), Gate 4 is located after TRR(Test Readiness Review) and Gate 5 is located before specification documentation submission. Conclusion: Off line QC(Quality Control) in development phase is necessary prior to on line QC(Quality Control) in p roduction phase. For the purpose of off line quality control, QFD(Quality Function Deployment) and Stage-gate process can be adopted.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.31-39
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• 2001

W polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail. $W/WN_x/poly-silicon$ adopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional $WSi_x$/Poly-silicon gate process. These results undoubtedly show that $W/WN_x/poly-silicon$ is the strongest candidate as a word line for Giga bit DRAM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.321-324
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• 1998

Pixel-Design Array Simulation Tool(PDAST) was used to profoundly the gate signal distortion and pixel changing capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the resistivity of gate line material on the pixel operations can be effectively analyzed. The gate signal delay, pixel charging ratio, level-shift of the pixel voltage were simulated with varying the resis5tivity of the gate line material. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.101-104
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• 2008

Too high stress of the bottom Mo layer of the gate line is thought to be the main reason for H-line mura. H-Line mura is eliminated effectively by changing the gate line metal structure from Mo/AlNd/Mo to AlNd/Mo. The new structure does not influence the panel's electrical characteristics.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.12
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• pp.768-772
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• 1999

A new TFT-LCD panel with air-bridge type gate to data line inter-crossing has been proposed and its characteristics have been measured. The proposed structure has air-gap between gate and data line inter-crossing. This air-bridge TFT-LCD panel has very small capacitance between gate and data line. The new panes structure achieves 9 times fast signal propagation compared with conventional panel, which enables to have enough design margin for 20-inch diagonal and larger size UXGA panel. We have examined thermal and mechanical durability of new panel to verify applicability for commercial AMLCD production. After TEOS and polyimide passivation, this panel withstood a thermal stress at $250^{\circ}C$ and a mechanical stress during the rubbing process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.8
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• pp.651-657
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• 2000

The notching effect in etching of undoped amorphous silicon gate had different characteristics and mechanism comparing with reported ones. The undoped amorphous silicon was etched by using HBr gas plasma. First in the region of small line width the potential increased as a result of ions in the exposed surface of oxide and the incident ions between the small line widths were deflected more wide range therefore the depth of notching was shallow and wide. Second in the region of large line width of gate electrons were charged on the top of photoresist and the side of gate a part of ions deflected. The deflected ions were partly charged positive on the side of gate and then these partly charged ions produced potential difference. Therefore ions stored up more at independent line than at dense line and notching became deeper by Br ion bombardments.

• Journal of the Korean Vacuum Society
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• v.8 no.4A
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• pp.490-495
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• 1999

In 0.18 $\mu \textrm m$ LOGIC device, the etch rate of NMOS polysilicons is different from that of PMOS polysilicons due to the state of polysilicon to manufacture gate line. To control the etch profile, we tested the ratio of $Cl_2$/HBr gas and the total chamber pressure, and also we reduced Back He pressure to get the vertical profile. In the case of manufacturing the gate photoresist line, we used Bottom Anti-Reflective Coating (BARC) to protect refrection of light. As a result we found that $CF_4O_2$ gas is good to etch BARC, because of high selectivity and good photoresist line profile after etching BARC. in the results of the characterization of plasma damage to the antenna effect of gate oxide, NO type thin film(growing gate oxide in 0, ambient followed by an NO anneal) is better than wet type thin film(growing gate oxide in $0_2+H_2$ ambient).

• Journal of the Korean housing association
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• v.20 no.4
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• pp.1-9
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• 2009

In this study, an examination and an analysis are carried out on the forms and components of the access spaces of hotel entrances from the front gate of five star hotels in Jejudo, Korea. The results of the study are as follows. In terms of the arrangement of the hotel, city hotels with a relatively narrow site area are influenced by site shape, while resort hotels with a relatively wide site area are affected by the environment. However, the location of the front gate was determined by the access road from the outside. Therefore, forms of access space are related to the front gate, which is governed by the access road, and to the entrance, which is determined by the hotel arrangement. If the front gate is in line with the hotel entrance, a straight line and the hotel are arranged vertically to the front gate(side arrangement) or the hotel is arranged horizontally to the front gate, but if the entrance is not in line with the front gate, it appears as a curved shape. However, those who use their own cars have a variety of choices for access route depending on the location of the parking lot.

• Journal of IKEEE
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• v.25 no.4
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• pp.774-777
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• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.10-13
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• 2000

The notching effect in etching of un doped amorphous silicon gate had different characteristics and mechanism comparing with reported ones. The undoped amorphous silicon was etched by using HBr gas plasma, First, in the region of small line width, the potential was increased as a result of ions in the exposed surface of oxide, and the incident ions between the small line width were deflected more wide range, therefore the depth of notching was shallow and wide, Second, in the region of large line width of gate, electrons were charged on the top of photoresist and the side of gate, a part of ions deflected, The deflected ions were locally charged positive on the side of gate, and then the potential difference was produced, therefore, ions stored up more at independent line than at dense line, and nothing became deeper by Br ion bombardment.