• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.6-12
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• 1998

Thin film SOI(Silicon-on-insulator) device offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature, and so on. But these devices exhibit floating-body effet such as current kink which inhibits the proper device operation. In this paper, the SOI NMOSFET with a T-type gate structure is proposed to solve the above problem. To simulate the proposed device with TSUPREM-4, the part of gate oxide was considered to be 30nm thicker than the normal gate oxide. The I-V characteristics were simulated with 2D MEDICI. Since part of gate oxide has different oxide thickness, the gate electric field strength is not same throughout the gate and hence the impact ionization current is reduced. The current kink effect will be reduced as the impact ionization current drop. The reduction of current kink effect for the proposed device structure were shown using MEDICI by the simulation of impact ionization current, I-V characteristics, and hole current distribution.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1965-1967
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• 1999

We have investigated the electrical characteristics of the poly-Si TFT's with the novel gate insulator structure. The gate insulator makes the offset region to reduce leakage current, and the electrical characteristics are obtained by employing Virtual Wafer Fab. simulator. As increases the gate insulator thickness above the offset region of this structure from $0{\AA}$ to $2000{\AA}$, the OFF state current at $V_G$=10V decrease by two orders in magnitude while ON state current doesn't decrease significantly. ON/OFF current ratios for conventional device and the proposed device with $2000{\AA}$ gate insulator thickness are $1.68{\times}10^5$ and $1.07{\times}10^7$, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.72-80
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• 1993

We fabricated 0.3um gate length inverse-T gate MOS(ITMOS) and conventional lightly doped drain oxide spacer MOS(LDDMOS), and studied electrical characteristics for comparison. Threshold voltage of 0.3um gate length device was 0.58 V for ITMOS and 0.6V for LDDMOS. Measured subthreshold characteristics showed a slope of 85mV/decades for both ITLDD and LDDMOS. Maximum transconductance at V S1ds T=V S1gs T=3.3V was 180mS/mm for ITMOS and 163mS/mm for LDDMOS respectively. GIDL current was observed to be 0.1pA/um for ITOMS and 0.8pA/um for LDDMOS. Substrate current of ITMOS as a function of drain current was found to be reduced by a foactor of 2.5 compared with that of LDDMOS.

• Electrical & Electronic Materials
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• v.9 no.6
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• pp.558-563
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• 1996

We fabricated high voltage hydrogenerated amorphous silicon thin film transistors (a Si:H HVTFT) and investigated its temperature dependent characteristics of from 303 K to 363 K. The results show that the drain current was decreased at low gate voltage and increased at high gate voltage exponentially. According to the increasing the thickness of a Si layer, drain current increased. Difference of drain current at 363 K was increasd at the lower gate voltage and decreased at the higher gate voltage. When the drain and gate voltage of 100 V applied, the drain current increased linearly with rise temperature.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12
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• pp.1065-1070
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• 2003

HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.

• ETRI Journal
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• v.44 no.3
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• pp.504-511
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• 2022

Monte Carlo simulations show that, as temperature increases, the average kinetic energy of channel electrons in a GaN transistor first decreases and then increases. According to the calculations, the relative energy change reaches 40%. This change leads to a reduced barrier height due to quantum coupling among the three-dimensional motions of channel electrons. Thus, an analysis and physical model of the gate leakage current that includes drift velocity is proposed. Numerical calculations show that the negative and positive temperature dependence of gate leakage currents decreases across the barrier as the field increases. They also demonstrate that source-drain voltage can have an effect of 1 to 2 orders of magnitude on the gate leakage current. The proposed model agrees well with the experimental results.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.23-30
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• 1993

Hydrogenation on the top gate and bottom gate Poly-Si TET's was performed by using Nh$_{3}$ plasma and annealing SiN film deposited by PECVD and then the electric characteristics on Poly-Si TET were investigated. As the time of NA$_{3}$ plasma treatment increaes, on/off current ratio gradually increases and the swing value decreases. The trap densities of graim boundaries in Poly-Si decrease very much during the inital 20min of hydrogenation time, and the decreasing scale becomes smaller after 20 min. The electric characteristics of the top gate TFT are better than those of the bottom gate TFT, it is considered due to the defects at the interface between the Poly-Si and the underlayer, SiO$_{2}$. After NH$_{3}$ plasma was treated for 2 hours for the top gate TFT, as the aging time atroon temperature increases on current was not scacely changed and off current decreases more than 1 order. Gate current density recovers to original value after the aging treatment for 8 days and then the electric characteristics are finally improved. It is suggested that the degraded characteristics of gate oxide are improved, from the variations of C-V characteristics with aging time. For the hydrogenation of isothermal and isochronal annealing SiN film deposited by PECVD, the characteristics of Poly-Si TFT are improved with increasing annealing temperature and are not largely changed with increasing annealing time. This results is good in agreement with the hydrogen reduction in Sin film as variations of annealing temperature and time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.145-152
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• 2003

Electrical gate and drain characteristics of double heterostructure InAlAs/InGaAs pseudomorphic HEMTs have been investigated under sub-bandgap photonic excitation ($hv). Drain $(V_{DS})-,{\;}gate($V_{DS})-$, and optical power($P_{opt}$)-dependent variation of the abnormal gate leakage current and associated physical mechanisms in the PHEMTs have been characterized. Peak gate voltage ($V_{GS,P}$) and the onset voltage for the impact ionization ($V_{GS.II}$) have been extracted and empirical model for their dependence on the $V_{DS}$ and $P_{opt} have been proposed. Anomalous gate and drain current, both under dark and under sub-bandgap photonic excitation, have been modeled as a parallel connection of high performance PHEMT with a poor satellite FET as a parasitic channel. Sub-bandgap photonic characterization, as a function of the optical power with $h\nu=0.799eV$, has been comparatively combined with those under dark condition for characterizing the bell-shaped negative humps in the gate current and subthreshold drain leakage under a large drain bias.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.423-430
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating $n^{+}$ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating $n^{+}$ zones, the transistor channel region is split into four zones with different lengths defined by a floating $n^{+}$ region. This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA while that of the conventional dual-gate structure is 0.5 mA at a 12 V drain voltage and a 7 V gate voltage. This results show a $80 {\%}$ enhancement in on-current by adding two floating $n^{+}$ zones. Moreover we observed the reduction of electric field In the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.