• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.39-49
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• 2008

AEA and ARIA are next generation standard block cipher of US and Korea, respectively, and these algorithms are used in various fields including smart cards, electronic passport, and etc. This paper addresses the first efficient unified hardware architecture of AES and ARIA, and shows the implementation results with 0.25um CMOS library. We designed shared S-boxes based on composite filed arithmetic for both algorithms, and also extracted common terms of the permutation matrices of both algorithms. With the $0.25-{\mu}m$ CMOS technology, our processor occupies 19,056 gate counts which is 32% decreased size from discrete implementations, and it uses 11 clock cycles and 16 cycles for AES and ARIA encryption, which shows 720 and 1,047 Mbps, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.5
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• pp.2317-2321
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• 2011

This paper is proposed new data crytoblock algorithm based on the private key cryptoalgorithim with existed other cryptography algorithims. Therefore new crytoblock design and simulation using the common Synopsys and ALTERA Max+ PlusII Ver.10.1. As a simulation result, new data crytoblock have gate counting 640Mbps at the 40M hz. We thought that proposed new data crytoblock adapt real time information security.

• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.177-181
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• 2008

The more improved the Internet and the information technology, the stronger cryptographic system is required which can satisfy the information security on the platform of personal hand-held devices or smart card system. This paper introduces a case study of designing an elliptic curve cryptographic processor of a high performance that can be suitably used in a wireless communicating device or in an embedded system. To design an efficient cryptographic system, we first analyzed the operation hierarchy of the elliptic curve cryptographic system and then implemented the system by adopting a serial cell multiplier and modified Euclid divider. Simulation result shows that the system was correctly designed and it can compute thousands of operations per a second. The operating frequency used in simulation is about 66MHz and gate counts are approximately 229,284.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.42-46
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• 2010

Encapsulation for information security is often carried out in Galois field in the form of arithmetic operations. This paper proposes how to efficiently perform exponentiation of arithmetic information on Galois field. Especially, by improving an existing bit-parallel exponentiator to exclude elements with heavy gate counts and to take advantage of system constants, this paper proposes how to implement a VLSI architecture with high performance even for large m.

• Journal of applied mathematics & informatics
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• v.39 no.5_6
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• pp.859-882
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• 2021

In the proposed paper, a new algorithm based on Nonlinear Feedback Shift Register (NLFSR) and modified RC4A (Rivest Cipher 4A) cipher is introduced. NLFSR is used for image pixel scrambling while modified RC4A algorithm is used for pixel substitution. NLFSR used in this algorithm is of order 27 with maximum period 2^27-1 which was found using Field Programmable Gate Arrays (FPGA), a searching method. Modified RC4A algorithm is the modification of RC4A and is modified by introducing non-linear rotation operator in the Key Scheduling Algorithm (KSA) of RC4A cipher. Analysis of occlusion attack (up to 62.5% pixels), noise (salt and pepper, Poisson) attack and key sensitivity are performed to assess the concreteness of the proposed method. Also, some statistical and security analyses are evaluated on various images of different size to empirically assess the robustness of the proposed scheme.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.3
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• pp.465-475
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• 2022

Due to the impact of COVID-19, people are paying attention to convenience and health, and the use of IoT devices to help them is increasing. In order to embed a lightweight security element in IoT devices that need to handle sensitive information even with limited resources, the development of a lightweight S-box is essential. Until 2021, it was common to develop a lightweight 4-bit S-box by a heuristic method, and to develop an extended structure or repeat the same operation for a larger size lightweight S-box. However, in January 2022, a paper that proposed a heuristic algorithm to find an 8-bit S-box with better differential uniformity and linearity than the S-box generated with an MISTY extended structure, although non-bijective, was published [1]. The heuristic algorithm proposed in this paper generates an S-box by adding AND operations one by one. Whenever an AND operation is added, they use a method that pre-removes the S-box for which the calculated differential uniformity does not reach the desired criterion. In this paper, we improve the performance of this heuristic algorithm. By increasing the amount of pre-removal using not only differential uniformity but also other differential property, and adding a process of calculating linearity for pre-removing, it is possible to satisfy not only differential security but also linear security.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.84-95
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• 2006

In H/W implementation for the finite field the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. In this paper, we propose a new, simpler, parallel multiplier over $GF(2^m)$ having a Gaussian normal basis of type k, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{mk})$ containing a type-I optimal normal basis. For k=2,4,6 the time and area complexity of the proposed multiplier is the same as tha of the best known Reyhani-Masoleh and Hasan multiplier.

• Journal of IKEEE
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• v.24 no.2
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• pp.468-474
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• 2020

This paper describes the hardware implementation of SPECK, a lightweight block cipher algorithm developed for the security of applications with limited resources such as IoT and wireless sensor networks. The block cipher SPECK crypto-core supports 8 block/key sizes, and the internal data-path was designed with 16-bit for small gate counts. The final round key to be used for decryption is pre-generated through the key initialization process and stored with the initial key, enabling the encryption/decryption for consecutive blocks. It was also designed to process round operations and key scheduling independently to increase throughput. The hardware operation of the SPECK crypto-core was validated through FPGA verification, and it was implemented with 1,503 slices on the Virtex-5 FPGA device, and the maximum operating frequency was estimated to be 98 MHz. When it was synthesized with a 180 nm process, the maximum operating frequency was estimated to be 163 MHz, and the estimated throughput was in the range of 154 ~ 238 Mbps depending on the block/key sizes.