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A Design of AES-based WiBro Security Processor  

Kim, Jong-Hwan (PixelPlus Inc.)
Shin, Kyung-Wook (School of Electronic Eng., Kumoh National Institute of Technology)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.7, 2007 , pp. 71-80 More about this Journal
Abstract
This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.
Keywords
WiBro; Security Processor; AES; Modes of Operation; Authentication; key wrap/unwrap;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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