• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 춘계종합학술대회 A
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• pp.105-110
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• 2008

식각 형상비에 의해 경사형 스페이스를 갖는 도핑 산화막을 이용한 LDD 영역을 갖도록 제작한 다결정 TFT의 새로운 구조를 제안한다. 소자 특성의 신뢰성을 위해 수소($H_2$)와 수소/플라즈마 처리 공정으로 다결정 실리콘에 수소 처리시킨 n-채널 다결정 실리콘 TFT 소자를 제작하였다. 소자에 최대 누설전류의 게이트 전압 조건에서 소자에 스트레스를 인가시켰다. 게이트 전압 스트레스 조건에 의해 야기되는 열화 특성인자들은 드레인 전류, 문턱전압($V_{th}$), 부-문턱전압 기울기(S), 최대 전달 컨덕턴스($g_m$), 그리고 파워인자 값을 측정/추출하였으며, 수소처리 공정이 소자 특성의 열화 결과에 미치는 관계를 분석하였다. 특성 파라미터의 분석 결과로써, 수소화 처리시킨 n-채널 다결정 실리콘 박막 트랜지스터에서 열화특성의 원인들은 다결정 실리콘/산화막의 계면과 다결정 실리콘의 그레인 경계에서 실리콘-수소 본드의 해리에 의한 현수 본드의 증가이었다. 이 증가가 소자의 핫-캐리어와 결합으로 개선된 열화 특성의 원인이 되었다. 따라서 새로 제안한 다결정 TFT의 구조는 제작 공정 단계가 간단하며, 소자 특성에서 누설전류가 드레인 영역 근처 감소된 수평 전계에 의해 감소되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

• 한국통신학회논문지
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• 제35권1A호
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• pp.80-86
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• 2010

본 논문은 게이트 채널 길이 0.13 [${\mu}m$]의 p-MOS 트랜지스터에서 음 바이어스 온도 불안정(NBTI) 전류 스트레스 인가에 의한 게이트유기 드레인 누설(GIDL) 전류를 측정 분석하였다. NBTI 스트레스에 의한 문턱전압의 변화와 문턱전압아래 기울기와 드레인 전류 사이에 상관관계로부터, 소자의 특성 변화의 결과로 열화에 대한 중요한 메카니즘이 계면 상태의 생성과 관련이 있다는 것을 분석하였다. GIDL 전류의 측정 결과로부터, NBTI 스트레스에 기인한 계면상태에서 전자-정공 쌍의 생성이 GIDL 전류의 증가의 결과를 도출하였다. 이런 결과로 부터, 초박막 게이트 산화막 소자에서 NBTI 스트레스 후에 증가된 GIDL 전류를 고려해야만 한다. 또한, 동시에 신뢰성 특성과 직류 소자 성능의 고려가 나노 크기의 CMOS 통신회로 설계의 스트레스 파라미터들에서 반드시 있어야 한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.345-345
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• 2010

1T-DRAM cell with solid phase (SPC) crystallized poly-Si thin film transistor was fabricated and electrical characteristics were evaluated. The fabricated device showed kink effect by negative back bias. Kink current is due to the floating body effect and it can be used to memory operation. Current difference between "1" state and "0" state was defined and the memory properties can be improved by using gate induced drain leakage (GIDL) current.

• EDISON SW 활용 경진대회 논문집
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• 제4회(2015년)
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• pp.343-346
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• 2015

Ultra-thin body transistor is one of the emerging devices since it control leakage current flows through substrate. In addition, it can be operated by double gates, thus, its on/off current ratio is higher than conventional counterpart. In this paper, we design and investigate a CMOS inverter based on ultra-thin body MOSFETs to estimate its performance in real application. NEGF (non-equilibrium Green's function) method is used to obatain relationship between drain current and voltage. DC transfer is extracted from the relationship, and FO4 (fanout-of-4) propagation delay is reported as 5.1 ps estimated by a simple model.

• Journal of Power Electronics
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• 제17권3호
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• pp.621-631
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• 2017

A KY converter integrated with a conventional synchronously rectified (SR) boost converter and a coupled inductor is presented in this paper. This improved KY converter has the following advantages: 1) the two converters use common switches; 2) the voltage gain of the KY converter can be improved due to the integration of a boost converter and a coupled inductor; 3) the leakage inductance of the coupled inductor is utilized to achieve zero voltage switching (ZVS); 4) the current stress on the charge pump capacitors and the decreasing rate of the diode current can be limited due to the use of the coupled inductor; and 5) the output current is non-pulsating. Moreover, the active switches are driven by using one half-bridge gate driver. Thus, no isolated driver is needed. Finally, the operating principle and analysis of the proposed converter are given to verify the effectiveness of the proposed converter.

• 한국재료학회지
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• 제14권8호
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• pp.542-546
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• 2004

We report a new fabrication process for high performance triode type CNT field emitters and their superior electrical properties. The CNT-based triode-type field emitter structure was fabricated by the conventional semiconductor processes. The keys of the fabrication process are spin-on-glass coating and trim-and-leveling of the carbon nanotubes grown in trench structures by employing a chemical mechanical polishing process. They lead to strong adhesion and a uniform distance from the carbon nanotube tips to the electrode. The measured emission property of the arrays showed a remarkably uniform and high current density. The gate leakage current could be remarkably reduced by coating of thin $SiO_{2}$ insulating layer over the gate metal. The field enhancement factor(${\beta}$) and emission area(${\alpha}$) were calculated from the F-N plot. This process can be applicable to fabrication of high power CNT vacuum transistors with good electrical performance.

• 반도체디스플레이기술학회지
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• 제16권2호
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• pp.66-69
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• 2017

In this paper, solution based Indium Zinc Oxide thin film transistors (IZO TFTs) were fabricated with PVP gate dielectric. To enhance the electrical properties, UV-O3 treatment is proposed on solution based IZO TFTs. The gate leakage current and interface trap density is compatible with conventional ZnO-based TFT with inorganic gate insulator. Especially, the UV-treated device shows improved electrical characteristics compared to the untreated device. These results can be explained by X-ray photoelectron spectroscopy (XPS) analysis, which shows that the oxygen vacancy of UV-O3 treatment is higher than that of no treatment.

• Current Applied Physics
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• 제18권12호
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• pp.1546-1552
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• 2018

The polymer nanocomposite as a gate dielectric film was prepared via sol-gel method. The formation of crosslinked structure among nanofillers and polymer matrix was proved by Fourier transform infrared spectroscopy (FT-IR). Differential thermal analysis (DTA) results showed significant increase in the thermal stability of the nanocomposite with respect to that of pure polymer. The nanocomposite films deposited on the p- and n-type Si substrates formed very smooth surface with rms roughness of 0.045 and 0.058 nm respectively. Deconvoluted $Si_{2s}$ spectra revealed the domination of the Si-OH hydrogen bonds and Si-O-Si covalence bonds in the structure of the nanocomposite film deposited on the p- and n-type Si semiconductor layers respectively. The fabricated n-channel field-effect-transistor (FET) showed the low threshold voltage and leakage currents because of the stronger connection between the nanocomposite and n-type Si substrate. Whereas, dominated hydroxyl groups in the nanocomposite dielectric film deposited on the p-type Si substrate increased trap states in the interface, led to the drop of FET operation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.