• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.71-72
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• 2006

플라스틱 기판 위에 유도 결합 플라즈마 화학적 기상 증착장치 (Inductively Coupled Plasma Chemicai Vapor Deposition, ICP-CVD) 를 사용하여 실리콘 산화막 ($SiO_2$)을 증착하고, 엑시머레이저 어널링 (Excimer Laser Annealing, ELA) 과 $N_{2}O$ 플라즈마 전처리를 통해, 전기용량-전압(Capacitance-Voltage, C-V) 특성과 항복 전압장 (Breakdown Voltage Field) 과 같은 전기적 특성을 개선시켰다. 에너지 밀도 $250\;mJ/cm^2$ 의 엑시머 레이저 어닐링은 실리콘 산화막의 평탄 전압 (Flat Band Voltage) 을 0V에 가까이 이동시키고, 유효 산화 전하밀도 (Effective Oxide Charge Density)를 크게 감소시킨다. $N_{2}O$ 플라즈마 전처리를 통해 항복 전압장은 6MV/cm 에서 9 MV/cm 으로 향상된다. 엑시머 레이저 어닐링과 $N_{2}O$ 플라즈마 전처리를 통해 평탄 전압은 -9V 에서 -1.8V 로 향상되고, 유효 전하 밀도 (Effective Charge Density) 는 $400^{\circ}C$에서 TEOS 실리콘 산화막을 증착하는 경우의 유효 전하 밀도 수준까지 감소한다.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.34-35
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• 2006

Transparent ZnO thin film transistor (TFT) is fabricated on the glass substrates. The device consists of a high mobility intrinsic ZnO as a semiconductor active channel, Ga doped ZnO (GZO) as an electrode, $HfO_2$ as a gate insulator. GZO and $HfO_2$ layers are prepared by using a pulsed laser deposition and intrinsic ZnO layers are fabricated by using an rf-magnetron sputtering, respectively. The transparent TFT is highly transparent (> 87 %) and exhibits n-channel, enhancement mode behavior with a field-effect mobility as large as $11.7\;cm^2/Vs$ and a drain current on-to-off ratio of about $10^5$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.6
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• pp.28-33
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• 1985

ISFETS for physiological applications have been developed using the techniques for integrated circuit fabrication. The silicon nitride layer was used as a H+ sensing membrane. However, K+, Na+ and Ca++ sensing ISFETS were fabricated by forming tach specification sensing membranes over the silicon nitride gate insulator. The sensitivities of the fabricated devices were very good. The typical values of measured sentivities were iEmV/pH, 42mv1, pH,5 gmV/pNa and 28mv1p0a. However, the selectivity and stability should be somewhat improved for practical physiological uses with good reliability. The response times were, less than one second, short enough for the practical uses in physiological applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.16-23
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• 2007

For a fully depleted SOI type symmetric double gate MOSFET, a simple expression for the threshold voltage has been derived in a closed-form To solve analytically the 2D Poisson's equation in a silicon body, the two-dimensional potential distribution is assumed approximately as a polynomial of fourth-order of x, vertical coordinate perpendicular to the silicon channel. From the derived expression for the surface potential, the threshold voltage can be obtained as a simple closed-form. Simulation result shows that the threshold voltage is exponentially dependent on channel length for the range of channel length up to $0.01\;[{\mu}m]$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.8
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• pp.479-483
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• 2017

The effect of $NH_3$ plasma treatment on device characteristics was confirmed for an optimized thin film transistor of poly-Si formed by ELA. When C-V curve was checked for MIS (metal-insulator-silicon), Dit of $NH_3$ plasma treated and MIS was $2.7{\times}10^{10}cm^{-2}eV^{-1}$. Also in the TFT device case, it was decreased to the sub-threshold slope of 0.5 V/decade, 1.9 V of threshold voltage and improved in $26cm^2V^{-1}S^{-1}$ of mobility. Si-N and Si-H bonding reduced dangling bonding to each interface. When gate bias stress was applied, the threshold voltage's shift value of $NH_3$ plasma treated device was 0.58 V for 1,000s, 1.14 V for 3,600s, 1.12 V for 7,200s. As we observe from this quality, electrical stability was also improved and $NH_3$ plasma treatment was considered effective for passivation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.743-746
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• 2000

Metal-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/$LiNbO_3$/Si structure were successfully fabricated. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V) curve was about 8.2. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$$1O^{-8}$A/$cm^2$ order at the electric field of 500kV/cm. The dielectric constant of $LiNbO_3$film on AIN/Si structure was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500kV/cm was about 5.6$\times$ $1O^{13}$ $\Omega$.cm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.110-111
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• 2006

이중 에피층을 가지는 SOI (Silicon-On-Insulator) RESURF(REduced SURface Field) LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자의 에피층 두께에 따른 항복전압 특성을 분석하였다. 이중 에 피층 구조를 가지는 SOI RESURF LIGBT 소자는 전하보상효과를 얻기 위해 기존 LIGBT 소자의 n 에피로 된 영역을 n/p 에피층의 이중 구조로 변경한 소자로 n/p 에피층 영역내의 전하간 상호작용에 의해 에피 영역 전체가 공핍됨으로써 높은 에피 영역농도에서도 높은 항복전압을 얻을 수 있는 소자이다. 본 논문에서는 LIGBT 에피층의 전체 두께와 농도를 고정한 상태에서 n/p 에피층의 두께가 변하는 경우에 항복전압 특성의 변화에 대해 simulation을 통해 분석하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.6
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• pp.466-468
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• 2009

The metal-insulator-silicon (MIS) capacitors with $SiO_2$ and high-k dielectrics ($HfO_2$, $Al_2O_3$) were fabricated, and the current-voltage characteristics were investigated. Especially, an effective barrier height between metal gate and dielectric was extracted by using Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot of quantum mechanical(QM) modeling. The calculated barrier heights of thermal $SiO_2$, ALD $SiO_2$, $HfO_2$ and $Al_2O_3$ are 3.35 eV, 0.6 eV, 1.75 eV, and 2.65 eV, respectively. Therefore, the performance of non-volatile memory devices can be improved by using engineered tunnel barrier which is considered effective barrier height of high-k materials.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.167-169
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• 2016

The structure guide lines of pocket tunnel field effect transistor(TFET) considering Line and Point tunneling are introduced. As the pocket doping concentration or thickness increase, on-current $I_{on}$ increases. As the pocket thickness or gate insulator increase, subthreshold swing(SS) increases. Optimal structure reducing the hump effects should be proposed in order to enhance SS.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.37-42
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• 2006

The preparation and processing of PVP-gate insulators on the device performance have been studied in the fabrication of organic thin film transistors (OTFTs). One of polyvinyl series, poly-4-vinyl phenol(PVP) was used as a solute and propyleneglycol monomethyl etheracetate(PGMEA) as a solvent in the formation of organic gate solutions. The cross-linking of organic insulators was also attempted by adding the thermosetting material, poly (melamine-co-formaldehyde) as a hardener in the compounds. From the measurements of electrical insulating characteristics of metal-insulator-metal (MIM) samples, PVP-based insulating layers showed lower leakage current according to the increase of concentration of PVP and poly (melamine-co-formaldehyde) to PGMEA in the formation of organic solutions. The PVP(20 wt%) copolymer with composition of 20 wt% PVP to PGMEA and cross-linked PVPs in which 5 wt% and 10 wt% poly (melamine-co-formaldehyde) hardeners had been additional]y mixed into PVP(20 wt%) copolymers were used as gate dielectrics in the fabrication of OTFTs, respectively. In our experiments, the maximum field effect mobility of $0.31cm^2/Vs$ could be obtained in the 5 wt% cross-linked PVP(20 wt%) device and the highest on/off current ratio of $1.92{\times}10^5$ in the 10 wt% cross-linked PVP(20 wt%) device.