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http://dx.doi.org/10.4313/JKEM.2009.22.6.466

Tunneling Properties in High-k Insulators with Engineered Tunnel Barrier for Nonvolatile Memory  

Oh, Se-Man (광운대학교 전자재료공학과)
Jung, Myung-Ho (광운대학교 전자재료공학과)
Park, Gun-Ho (광운대학교 전자재료공학과)
Kim, Kwan-Su (광운대학교 전자재료공학과)
Chung, Hong-Bay (광운대학교 전자재료공학과)
Lee, Young-Hie (광운대학교 전자재료공학과)
Cho, Won-Ju (광운대학교 전자재료공학과)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.22, no.6, 2009 , pp. 466-468 More about this Journal
Abstract
The metal-insulator-silicon (MIS) capacitors with $SiO_2$ and high-k dielectrics ($HfO_2$, $Al_2O_3$) were fabricated, and the current-voltage characteristics were investigated. Especially, an effective barrier height between metal gate and dielectric was extracted by using Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot of quantum mechanical(QM) modeling. The calculated barrier heights of thermal $SiO_2$, ALD $SiO_2$, $HfO_2$ and $Al_2O_3$ are 3.35 eV, 0.6 eV, 1.75 eV, and 2.65 eV, respectively. Therefore, the performance of non-volatile memory devices can be improved by using engineered tunnel barrier which is considered effective barrier height of high-k materials.
Keywords
Non-volatile memory; Effective barrier height; High-k;
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