• 제목/요약/키워드: Gate Dielectric

검색결과 454건 처리시간 0.026초

Characterization of Thin Film Transistor using $Ta_2O_5$ Gate Dielectric

  • Um, Myung-Yoon;Lee, Seok-Kiu;Kim, Hyeong-Joon
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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    • pp.157-158
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    • 2000
  • In this study, to get the larger drain current of the device under the same operation condition as the conventional gate dielectric SiNx thin film transistor devices, we introduced new gate dielectric $Ta_2O_5$ thin film which has high dielectric constant $({\sim}25)$ and good electrical reliabilities. For the application for the TFT device, we fabricated the $Ta_2O_5$ gate dielectric TFT on the low-temperature-transformed polycrystalline silicon thin film using the self-aligned implantation processing technology for source/drain and gate doping. The $Ta_2O_5$ gate dielectric TFT showed better electrical performance than SiNx gate dielectric TFT because of the higher dielectric constant.

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4H-SiC UMOSFET의 gate dielectric 물질에 따른 온도 신뢰성 분석 (Temperature reliability analysis according to the gate dielectric material of 4H-SiC UMOSFET)

  • 정항산;허동범;김광수
    • 전기전자학회논문지
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    • 제25권1호
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    • pp.1-9
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    • 2021
  • 본 논문에서는 고전압, 고전류 동작에 적합한 4H-SiC UMOSFET에 대해서 연구하였다. 일반적으로 SiO2는 SiC MOSFET에서 gate dielectric으로 가장 많이 사용되는 물질이다. 하지만 4H-SiC보다 유전 상수 값이 2.5배 낮아서 높은 전계를 갖게 되므로 SiO2/SiC 접합 부분에서 열악한 특성을 갖는다. 따라서 high-k 물질을 gate dielectric으로 적용한 소자를 SiO2를 적용한 소자와 TCAD 시뮬레이션을 통해 전기적 특성을 비교하였다. 그 결과 BV 감소, VTH 감소, gm 증가, Ron 감소를 확인하였다. 특히 온도가 300K일 때, Al2O3와 HfO2의 Ron은 66.29%, 69.49%가 감소하였으며 600K일 때도 39.71%, 49.88%가 감소하였다. 따라서 Al2O3와 HfO2가 고전압 SiC MOSFET의 gate dielectric 물질로써 적합함을 확인하였다.

유기물과 유무기 혼합 폴리머 게이트 절연체를 사용한 유기 박막 트랜지스터의 특성 (Characteristics of Organic Thin Film Transistors with Organic and Organic-inorganic Hybrid Polymer Gate Dielectric)

  • 배인섭;임하영;조수헌;문송희;최원석
    • 한국전기전자재료학회논문지
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    • 제22권12호
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    • pp.1009-1013
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    • 2009
  • In this study, we have been synthesized the dielectric layer using pure organic and organic-inorganic hybrid precursor on flexible substrate for improving of the organic thin film transistors (OTFTs) and, design and fabrication of organic thin-film transistors (OTFTs) using small-molecule organic semiconductors with pentacene as the active layer with record device performance. In this work OTFT test structures fabricated on polymerized substrates were utilized to provide a convenient substrate, gate contact, and gate insulator for the processing and characterization of organic materials and their transistors. By an adhesion development between gate metal and PI substrate, a PI film was treated using $O_2$ and $N_2$ gas. The best peel strength of PI film is 109.07 gf/mm. Also, we have studied the electric characteristics of pentacene field-effect transistors with the polymer gate-dielectrics such as cyclohexane and hybrid (cyclohexane+TEOS). The transistors with cyclohexane gate-dielectric has higher field-effect mobility, $\mu_{FET}=0.84\;cm^2/v_s$, and smaller threshold voltage, $V_T=-6.8\;V$, compared with the transistor with hybrid gate-dielectric.

박막 게이트 절연체 위에서 Ta-Mo 합금의 안정성 (Stability of Ta-Mo alloy on thin gate dielectric)

  • 이충근;강영섭;서현상;홍신남
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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    • pp.9-12
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    • 2004
  • This paper investigated the stability of Ta-Mo alloy on thin gate dielectric. Ta-Mo alloy was deposited by using co-sputtering process after thermal growing of 3.4nm and 4.2nm silicon dioxide. When the sputtering power of Ta and Mo were 100W and 70W, respectively, the suitable work function for NMOS gate electrode, 4.2eV, could obtain. To prove interface thermal stability of thin film gate dielectric and Ta-Mo alloy, rapid thermal annealing was performed at $600^{\circ}C$ and $700^{\circ}C$ for 10sec in Ar ambient. The results of interface reaction were surveyed by change of silicon dioxide thickness and work function after annealing process. Also, the reliability of alloy gate and gate dielectric could be confirmed by quantity of leakage current. Ta-Mo alloy was showed low sheet resistance and thermal stability, namely, little change of gate dielectric and work function, after $700^{\circ}C$ annealing process.

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Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

  • Narang, Rakhi;Saxena, Manoj;Gupta, R.S.;Gupta, Mridula
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권3호
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    • pp.224-236
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    • 2013
  • This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.

Threshold Voltage Control of Pentacene Thin-Film Transistor with Dual-Gate Structure

  • Koo, Jae-Bon;Ku, Chan-Hoe;Lim, Sang-Chul;Lee, Jung-Hun;Kim, Seong-Hyun;Lim, Jung-Wook;Yun, Sun-Jin;Yang, Yong-Suk;Suh, Kyung-Soo
    • Journal of Information Display
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    • 제7권3호
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    • pp.27-30
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    • 2006
  • This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.

Graphene for MOS Devices

  • 조병진
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2012년도 춘계학술발표대회
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    • pp.67.1-67.1
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    • 2012
  • Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

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Threshold Voltage control of Pentacene Thin-Film Transistor with Dual-Gate Structure

  • Koo, Jae-Bon;Ku, Chan-Hoe;Lim, Sang-Chul;Lee, Jung-Hun;Kim, Seong-Hyun;Lim, Jung-Wook;Yun, Sun-Jin;Yang, Yong-Suk;Suh, Kyung-Soo
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.1103-1106
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    • 2006
  • We have presented a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_2O_3$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_2O_3$ as both a top gate dielectric and a passivation layer is reported. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_2O_3$ as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure has been successfully understood by an analysis of electrostatic potential.

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Spin coating 공정을 이용한 Polymethyl methacrylate (PMMA) 박막의 polymer gate dielectric layer로써의 특성평가 (Properties of Polymethyl methacrylate (PMMA) for Polymer Gate Dielectric Thin Films Prepared by Spin Coating)

  • 나문경;강동필;안명상;명인혜;강영택
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 춘계학술대회 논문집
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    • pp.29-32
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    • 2005
  • Poly (methyl methacrylate) (PMMA) is one of the promising representive of polymer gate dielectric for its high resistivity and sutible dielectric constant. PMMA (Mw=96700) films were prepared on p-Si by spin coating method. PMMA were coated compactively and flatly as observeed by AFM. MIS(Al/PMMA/p-Si) structure was made and capacitance-voltage (C-V) and current-voltage (I-V) measurements were done with PMMA films for different thermal treatment temperature. PMMA films were showed proper dielectric constant and breakdown voltage. Above the glass transition temperature PMMA films degraded. C-V measured at various frequencies, dielectric constant increased a little. The absence of hysteresis in the C-V characteristics, which eliminate the possibility of mobile charges in the PMMA films. The observed thermal stability, smooth surfaces, dielectric constant, I-V behavior implies PMMA formed by spin coating can be used as an efficient gate dielectric layer in OTFTs.

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원자층 식각을 이용한 Sub-32 nm Metal Gate/High-k Dielectric CMOSFETs의 저손상 식각공정 개발에 관한 연구

  • 민경석;김찬규;김종규;염근영
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.463-463
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    • 2012
  • ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.

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