• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.59-63
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• 2000

For the Mo-tip field emitter array, the method by which the geometrical structure of the gate insulator wall could be modified in order to improve field emission properties(turn-on voltage and gate leakage current). The device having a gate insulator of complex shape, which means the combined geometrical structure with round shape made by wet etching and vertical shape made by dry etching processes, was fabricated and the field emission properties of the three kinds of devices were compared. As a result, the electric field applied to tip apex could be increased and gate leakage current could be decreased by employing the gate insulator having geometrical wall structure of mixed shape. Finally, the obtained empirical results were analyzed by simulation of electric field distribution at/near the tip apex and gate insulator using SNU-FEAT simulator.

• 한국결정성장학회지
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• 제14권2호
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• pp.47-49
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• 2004

Gate protection $SiN_x$ as an alternative to a conventional re-oxidation process in Dynamic Random Access Memory devices is investigated. This process can not only protect the gate electrode tungsten against oxidation, but also save the thermal budget due to the re-oxidation. The protection $SiN_x$ process is applied to the poly-Si gate, and its device performance is measured and compared with the re-oxidation processed poly-Si gate. The results on the gate dielectric integrity show that etch damage-curing capability of protection $SiN_x$ is comparable to the re-oxidation process. In addition, the hot carrier immunity of the $SiN_x$ deposited gate is superior to that of re-oxidation processed gate.

• 한국전기전자재료학회논문지
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• 제30권2호
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• pp.63-66
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• 2017

This research was about shielded trench gate power MOSFET for low voltage and high speed. We used T-CAD tool and carried out process and device simulation for exracting design and process parameters. The exracted parameters was used to design shieled and conventional trench gate power MOSFET. And The electrical characteristics of shieled and conventional trench gate power MOSFET were compared and analyzed for their power device applications. As a result of analyzing electrical characteristics, the recorded breakdown voltages of both devices were around 120 V. The electric distributions of shielded and conventional trench gate power MOSFET was different. But due to the low voltage level, the breakdown voltage was almost same. And the other hand, the threshold voltage characteristics of shielded trench gate power MOSFET was superior to convention trench gate power MOSFET. In terms of on resistance characteristics, we obtained optimal oxied thickness of $3{\mu}m$.

• 한국전자통신학회논문지
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• 제5권1호
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• pp.88-92
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• 2010

본 연구에서는 기존의 반도체 공정을 이용하여 bottom gate, top gate구조의 탄소나노튜브 트랜지스터를 제작하였다. 게이트 특성에 따른 특성을 연구하기 위하여 열화학 기상 증착법(CVD)으로 탄소나노튜브를 디바이스에 직접 성장시키고, 탄소나노튜브의 성장 특성 및 I-V동작 특성을 분석하였다. 제작된 탄소나노튜브 FET는 p-type, 즉 hole이 다수 캐리어로 존재하는 트랜지스터이며 구동전압에 따라 conductance 변화하는 특성을 보였다.

• 한국유체기계학회 논문집
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• 제11권1호
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• pp.46-51
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• 2008

A stability analysis has been made for a newly designed gate of intake tower of reservoir. The analysis is composed of finding the natural frequency of the gate and the frequency induced by water flowing over and through the gate. ANSYS is employed to calculate the natural frequency of the gate and SC/Tetra is utilized for calculating flow field around the gate, which in turn gives the frequency of pressure force fluctuation on the gate. In addition to the safety analysis, the present study presents how the gate selectively intakes a muddy water layer located in the middle depth of reservoir.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1286-1288
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• 1997

In this study, partially-depleted SOI MOSFET with multi-gate was fabricated on p-type SIMOX(Seperation by Implanted Oxygen). As increase the number of its gate, increase the breakdown voltage. But kink effect was not affected by the number of its gate. However, it is known that the asymmetric gate structure reduce kink effect. So if asymmetric multi-gate applied to partially-depleted SOI MOSFET, it is expected that the breakdown voltage of SOI MOSET with asymmetric multi-gate is higher than that of SOI MOSFET with single gate and that kink effect is reduced by SOI MOSFET with asymmetric multi-gate.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2002년도 추계종합학술대회
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• pp.486-489
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• 2002

본 논문에서는 50nm 이하의 double gate MOSFET의 특성을 조사하였다. 1.5V의 main gate 전압과 3V의 side gate 전압이 인가될 때 I-V 특성으로부터 IDsat=510$\mu$A/$\mu\textrm{m}$을 얻을 수 있었다. 이때, 전달 컨덕턴스는 111$\mu$A/V, subthreshold slope는 86mV/dec, DIBL값은 51.3mV이다. 그밖에 TCAD tool이 소자 시뮬레이터로서 적합함을 나타내었다.

• E2M - 전기 전자와 첨단 소재
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• 제10권1호
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• pp.26-32
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• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• 한국정보통신학회논문지
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• 제6권7호
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• pp.1074-1078
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• 2002

본 논문에서는 main gate(MG)와 side gate(SG)를 갖는 double gate(DG) MOSFET를 디자인하고 TCAD를 이용하여 시뮬레이션하였다. MG와 SG의 길이(LMG, LSG)는 각각 50nm, 70nm로 하였으며, MG와 SG의 전압(VMG, VSG)이 각각 1.5V, 3.0V일 때 드레인전압(VD)을 0에서 1.5V까지 변화시키면서 핀치오프특성을 조사하였다. LMG가 아주 작음에도 불구하고, 핀치-오프특성이 아주 좋게 나타났다. 이것은 DG MOSFET의 VMG가 게이트를 제어하는 역할을 잘 수행하여 나노 구조에서 유용한 구조임을 알 수 있었다.

• 대한전자공학회논문지SD
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• 제41권11호
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• pp.1-6
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• 2004

RFIC를 위한 Nanoscale MOSFET에서의 유효 게이트 저항을 직접 추출법으로 추출하여 다양한 게이트 길이에 대해 분석하였다. 추출된 유효 게이트 저항은 비교적 정확하면서 간소화된 모델을 통한 측정결과와 비교하여 10GHz 대역까지 잘 일치함을 확인하였다. 같은 공정기술로 제작된 소자들 중에서 reverse short channel 효과가 생기지 않는 긴 채널 MOSFET 소자의 경우에 일반적인 유효 게이트 저항에서와는 다른 인가전압 및 주파수 종속성을 가짐을 확인하였다. 특히, 문턱전압을 전후하여 주파수에 따라 상이한 결과를 나타내고 있으며, 게이트 인가전압이 문턱전압에 가까울 때 비이상적으로 큰 유효 게이트 저항값을 나타내었다. 이러한 특성은 직접추출법을 사용하는 RF MOSFET 모델링에 있어서 참고해야 할 중요한 특성이 될 것이다.