• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.2
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• Journal of IKEEE
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• v.22 no.2
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• pp.484-487
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• 2018

5 MeV proton-irradiation with total dose of $10^{15}/cm^2$ was performed on AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with various gate metals including Ni, TaN, W, and TiN to investigate the degradation characteristics. The positive shift of pinch-off voltage and the reduction of on-current were observed from irradiated HEMTs regardless of a type of gate materials. Hall and transmission line measurements revealed the reduction of carrier mobility and sheet charge concentration due to displacement damage by proton irradiation. The shift of pinch-off voltage was dependent on Schottky barrier heights of gate metals. Gate leakage and capacitance-voltage characteristics did not show any significant degradation demonstrating the superior radiation hardness of Schottky gate contacts on GaN.

• Journal of the Architectural Institute of Korea Planning & Design
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• v.34 no.5
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• pp.109-118
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• 2018

Noryang Temporary Palace was a place where king Jeongjo (1752-1800) would have lunch after crossing the Temporary Palace River on his way to Hwaseong Temporary Palace to worship at Hyeonryungwon, the tomb of his father, Sadoseja. The government offices in charge of ship bridge construction 'Jugyosa' and 'Byeoljangso' were located in the Temporary Palace. The central buildings of the Haenggung Palace, which ranged up to Yongyangbongjeojeong, were arranged to observe both 'Jugyosa' and 'Byeoljangso' from the Temporary Palace by lifting the ground from Sammun Gate to Yongyangbongjeojeong. Yongyangbongjeojeong, the center of Noryang Temporary Palace, features the style of royal palace architecture and functions of housing architecture. The 'Jugyosa' and 'Byeoljangso' buildings had eight quarters. According to the records, in addition, 15 wood sheds, 5 rice hubs, 3 barns, 1 side gate quarter, 1 front gate, 70 separate sheds, 2 suragan temporary buildings, oesammun gate and hongsalmun gate were found. Such architectural layout is matched with the Temporary Palace Jugyohwaneodo Painting.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.4
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• pp.208-211
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• 2018

This paper details the design of a 1,200 V class trench gate field stop IGBT (insulated gate bipolar transistor) with a nano gate structure smaller than 1 um. Decreasing the size is important for lowering the cost and increasing the efficiency of power devices because they are high-voltage switching devices, unlike memory devices. Therefore, in this paper, we used a 2-D device and process simulations to maintain a gate width of less than 1 um, and carried out experiments to determine design and process parameters to optimize the core electrical characteristics, such as breakdown voltage and on-state voltage drop. As a result of these experiments, we obtained a wafer resistivity of $45{\Omega}{\cdot}cm$, a drift layer depth of more than 180 um, an N+ buffer resistivity of 0.08, and an N+ buffer thickness of 0.5 um, which are important for maintaining 1,200 V class IGBTs. Specially, it is more important to optimize the resistivity of the wafer than the depth of the drift layer to maintain a high breakdown voltage for these devices.

• Journal of IKEEE
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• v.22 no.1
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• pp.205-208
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• 2018

In this work, we performed reverse- and forward-gate bias stress tests on normally-off AlGaN/GaN high electron mobility transistors(HEMTs) with p-AlGaN-gate for reliability assessment. Inverse piezoelectric effect, commonly observed in Schottky-gate AlGaN/GaN HEMTs during reverse bias stress, was not observed in p-AlGaN-gate AlGaN/GaN HEMTs. Forward gate bias stress tests revealed distinct degradation of p-AlGaN-gate devices exhibiting sudden increase of gate leakage current. We suggest that forward gate bias stress tests should be performed to define the failure criteria and assess the reliability of normally off p-AlGaN-gate GaN HEMTs.

• Journal of Korea Water Resources Association
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• v.51 no.5
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• pp.405-415
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• 2018

Hydraulic variables such as discharge coefficient, gate opening, and upstream water depth are required to calculate the discharge of vertical lift gate. It is very important for a precise gate design, because it may affect the rest, to predict the behavior of gate opening during operation. In this study, an equation by which gate opening could be predicted with any upstream water depths was derived from the relation between the calculated value from buoyancy theory and measured one from experiment for a floating gate model. Downpull force was the reason for the differences between the calculated and the measured and it was verified using pressure coefficient. Also, the relation of discharge coefficient with gate opening ratios was derived. The derived relations were used for flood routing and it was realized that downpull force effect should be fully taken into account during gate design.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.732-741
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• 2018

In order to maximize the usable capacity of a BMS (battery management system) that uses several battery cells connected in series, a cell balancing technique that equips each cell with the same voltage is needed. In the active cell balancing circuit using a multi-winding transformer, a balancing circuit that transfers energy directly to the cell (cell-to-cell) is composed of a PMOS switch and a gate driving chip for driving the NMOS switch. The TLP2748 photocoupler and the TLP2745 photocoupler are required, resulting in increased cost and reduced integration. In this paper, instead of driving PMOS and NMOS switching devices by using photocoupler, we proposed 70V BCD process based PMOS gate driving circuit, NMOS gate driving circuit, PMOS gate driving circuit and NMOS gate driving circuit with improved switching time. ${\Delta}t$ of the PMOS gate drive switch with improved switching time was 8.9 ns and ${\Delta}t$ of the NMOS gate drive switch was 9.9 ns.

• Journal of IKEEE
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• v.22 no.1
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• pp.74-79
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• 2018

We analyzed the relationship between center potential and subthreshold swing (SS) of Junctionless Cylindrical Surrounding Gate (JLCSG) and Junctionless Double Gate (JLDG) MOSFET. The SS was obtained using the analytical potential distribution and the center potential, and SSs were compared and investigated according to the change of channel dimension. As a result, we observed that the change in central potential distribution directly affects the SS. As the channel thickness and oxide thickness increased, the SS increased more sensitively in JLDG. Therefore, it was found that JLCSG structure is more effective to reduce the short channel effect of the nano MOSFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.117-124
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• 2018

Junctionless amorphous InGaZnO thin film transistors with different film thickness have been fabricated. Their device performance parameters were extracted and gate oxide breakdown voltages were analyzed with different film thickness. The device performances were enhanced with increase of film thickness but the gate oxide breakdown voltages were decreased. The device performances were enhanced with increase of temperatures but the gate oxide breakdown voltages were decreased due to the increased drain current. The drain current under illumination was increased due to photo-excited electron-hole pair generation but the gate oxide breakdown voltages were decreased. The reason for decreased breakdown voltage with increase of film thickness, operation temperature and light intensity was due to the increased number of channel electrons and more injection into the gate oxide layer. One should decide the gate oxide thickness with considering the film thickness and operating temperature when one decides to replace the junctionless amorphous InGaZnO thin film transistors as BEOL transistors.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.142.1-142.1
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• 2018

This research presents a new field effect transistor (FET) by using liquid crystal gate dielectric with remote gate. The fabrication of thin-film transistors (TFTs) was used Indium tin oxide (ITO) for the source, drain, and gate electrodes, and indium gallium zinc oxide (IGZO) for the active semiconductor layer. 5CB liquid crystal was used for the gate dielectric material, and the remote gate and active layer were covered with the liquid crystal. The output and transfer characteristics of the LC-gated TFTs were investigated.