• Journal of the Institute of Electronics and Information Engineers
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• 제50권8호
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• pp.136-142
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• 2013

CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.

• The Journal of the Korea institute of electronic communication sciences
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• 제8권8호
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.187-187
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• 2012

Solution-processed metal-alloy oxides such as indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) has been extensively researched due to their high electron mobility, environmental stability, optical transparency, and solution-processibility. In spite of their excellent material properties, however, there remains a challenging problem for utilizing IZO or IGZO in electronic devices: the supply shortage of indium (In). The cost of indium is high, what is more, indium is becoming more expensive and scarce and thus strategically important. Therefore, developing an alternative route to improve carrier mobility of solution-processable ZnO is critical and essential. Here, we introduce a simple route to achieve high-performance and low-temperature solution-processed ZnO thin film transistors (TFTs) by employing alkali-metal doping such as Li, Na, K or Rb. Li-doped ZnO TFTs exhibited excellent device performance with a field-effect mobility of $7.3cm^2{\cdot}V-1{\cdot}s-1$ and an on/off current ratio of more than 107. Also, in case of higher drain voltage operation (VD=60V), the field effect mobility increased up to $11.45cm^2{\cdot}V-1{\cdot}s-1$. These all alkali metal doped ZnO TFTs were fabricated at maximum process temperature as low as $300^{\circ}C$. Moreover, low-voltage operating ZnO TFTs was fabricated with the ion gel gate dielectrics. The ultra high capacitance of the ion gel gate dielectrics allowed high on-current operation at low voltage. These devices also showed excellent operational stability.

• Applied Chemistry for Engineering
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• 제22권5호
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• pp.551-554
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• 2011

One of the key issues in the research of organic field-effect transistors (OFETs) is the low-voltage operation. To address this issue, we synthesized poly(styrene-r-benzocyclobutene-r-methyl methacrylate) (P(S-r-BCB-r-MMA)) as a thermally cross-linkable gate dielectrics. The P(S-r-BCB-r-MMA) showed high quality dielectric properties due to the negligible volume change during the cross-linking. The pentacene FETs based on the 34 nm-thick P(S-r-BCB-r-MMA) gate dielectrics operate below 5 V. The P(S-r-BCB-r-MMA) gate dielectrics yielded high device performance, i.e. a field-effect mobility of $0.25cm^2/Vs$, a threshold voltage of -2 V, an sub-threshold slope of 400 mV/decade, and an on/off current ratio of ${\sim}10^5$. The thermally cross-linkable P(S-r-BCB-r-MMA) will provide an attractive candidate for solution-processable gate dielectrics for low-voltage OFETs.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제65권1호
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• pp.73-80
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• 2016

The preliminary test for the dual mode plasma torch system was carried out to explore the operation properties in advance. The dual mode plasma torch system that is able to operate in transferred, non-transferred, or dual mode is very adequate for melting the mixed wastes including nonconductive materials such as concrete, asbestos, etc. since it exploits both the high efficiency of heat transfer to the melt in transferred mode and stable operation in non-transferred mode. Also, system operation including restarting is reliable and very easy. A stationary melter with a refractory structure was designed and manufactured considering the melting behavior of slags to minimize the refractory erosion. The power supply for the dual mode plasma torch system built with high power insulated gate bipolar transistor (IGBT) modules has functions for both current control and voltage control and is sufficient to suppress the harmonics during the operation of the plasma torch. The power supply provides two different voltages for transferred operation and non-transferred. It is confirmed that the operation voltage in transferred is always higher than non-transferred. The dual mode plasma torch system was successfully developed and is under operation for a melting experiment to optimize operation data.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.192-197
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• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• Journal of the Korea Society of Computer and Information
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• 제6권2호
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• pp.58-64
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• 2001

The quantity of container transportation of the world harbors is constantly increasing by 8.8％ per year until 2011. present port facilities will not satisfy it. So facility expansion is necessary. Because the processing cost in the harbor becomes to 30％ of total transportation expense, major ports in the world are making an effort in the automation facilities to solve the problems of higher labor costs and insufficient labor and to maximize the efficiency of the work and use of the land. Especially, the automation of the gate, which is the place of cargo's appearance and disappearance, the node which creates the information. is now rising as the important issue. In this study suggests more efficient design for port gate automation.

• Journal of information and communication convergence engineering
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• 제14권2호
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• pp.115-121
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• 2016

Currently there is a lack of literature on SPICE-level models of double-gate (DG) tunnel field-effect transistors (TFETs). A DG TFET compact model is presented in this work that is used to develop a SPICE model for DG TFETs implemented with Verilog-A language. The compact modeling approach presented in this work integrates several issues in previously published compact models including ambiguity about the use of tunneling parameters A_k and B_k, and the use of a universal equation for calculating the surface potential of DG TFETs in all regimes of operation to deliver a general SPICE modeling procedure for DG TFETs. The SPICE model of DG TFET captures the drain current-gate voltage (I_ds-V_gs) characteristics of DG TFET reasonably well and offers a definite computational advantage over TCAD. The general SPICE modeling procedure presented here could be used to develop SPICE models for any combination of structural parameters of DG TFETs.

• Journal of the Korea Academia-Industrial cooperation Society
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• 제11권2호
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• pp.485-490
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• 2010

We propose the equivalent circuit model including all parasitic components in input gate of sense amplifier of DDI DRAM with butting contact structure. We analysed the effect of parasitic schottky diode by using the proposed model in the operation of sense amplifier. The cause of single side fail and the temperature dependence of fail rate in DDI DRAM are due to creation of the parasitic schottky diode in input gate of sense amplifier. The parasitic schottky diode cause the voltage drop in input gate, and result in decreasing noise margin of sense amplifier. therefore single side fail rate increase.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제7권5호
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• pp.863-871
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• 2003

In this paper, we design a high stable Ku-band phase-locked dielectric resonant microwave oscillator with the gate voltage controls of p-HEMT. By adapting the nonlinear equivalent elements which affects phase noise of microwave oscillator, we optimize the nonlinear elements of p-HEMT to have low phase noise operation. Using the scattering parameters according to bias voltages, we designed the gate voltage control microwave dielectric resonant oscillator and phase-locked loop circuits is applied to have the high stable operations. Designed microwave oscillator as a local oscillator of digital microwave communication shows that output power is 9.17dBm at 10.75GHz and it's phase noise is -88dBc/Hz at 10KHz offset frequency.