Browse > Article
http://dx.doi.org/10.5573/ieek.2013.50.8.136

Matrix type CRC and XOR/XNOR for high-speed operation in DDR4 and GDDR5  

Lee, JoongHo (Department of Computer Science, Yongin University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.8, 2013 , pp. 136-142 More about this Journal
Abstract
CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.
Keywords
matrix type CRC; XOR/XNOR; DDR4; GDDR5; High-speed memory;
Citations & Related Records
연도 인용수 순위
  • Reference
1 D. Graham-Smith, "IDF: DDR3 won''t catch up with DDR2 during 2009," in PC Pro, Aug. 2008.
2 S. Yoon, B. Kim, Y. Kim, B. Chung, "A Fast GDDR5 Read CRC Calculation Circuit with Read DBI Operation," IEEE Asian Solid-Sate Circuits Conference, pp. 249-252, November, 2008.
3 Seung-Jun Bae, Kwang-Il Park, "An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion," IEEE Journal of Solid-State Circuits, Vol.43, pp. 121-131, January, 2008.   DOI   ScienceOn
4 K. Lin, C. Wu, "A Low-cost Realization of Multiple-input Exclusive-OR gates," ASIC Conference and Exhibit, Proceedings of the Eighth Annual IEEE International, pp. 307-10, September. 1995.
5 H. Bui, Y. Wang, and Y. Jiang, "New 4-Transistor XOR and XNOR Designs," in Proc. 2nd IEEE Asia Pacific Conf. ASICs, pp.25-8, August, 2000.
6 Kibong Koo, et al., "A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with Bank Group and x4 Half-Page Architecture" IEEE International Solid State Circuits Conference, pp. 40-41, Feb. 2012.
7 Kyomin Sohn, et al., "A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme" IEEE Journal of Solid State Circuits, Vol.48, pp. 168-177, Jan. 2013.   DOI   ScienceOn
8 Koopman, P. and Chakravarty T. "Cyclic Redundancy Code(CRC) Polynomial Selection For Embedded Networks" 2004 International Conference on Dependable Systems and Networks, pp. 145-154 28 June-1 July 2004.
9 H. Bui, Y. Wang, and Y. Jiang, "Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR-XNOR Gates," IEEE Transactions on Circuits and Systems II, Vol. 49, No. 1, pp. 25-0, January, 2002.   DOI   ScienceOn