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http://dx.doi.org/10.5573/ieek.2013.50.8.136

Matrix type CRC and XOR/XNOR for high-speed operation in DDR4 and GDDR5  

Lee, JoongHo (Department of Computer Science, Yongin University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.8, 2013 , pp. 136-142 More about this Journal
Abstract
CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.
Keywords
matrix type CRC; XOR/XNOR; DDR4; GDDR5; High-speed memory;
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