• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.237-244
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• 2013

A continuous, explicit drain-current equation for short-channel double-gate (DG) MOSFETs has been derived based on the explicit surface potential equation. The model is physically derived from Poisson's equation in each region of operation and adopted in the unified regional approach. The proposed model has been verified with numerical solutions, physically scalable with channel length and gate/oxide materials as well as oxide/channel thicknesses.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.855-858
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• 1998

Many semiconductive switches are operated in series for high voltage operation. The same number of gate drivers are needed to control all the switches, hence, the drivers cause high cost and system complexity. In this study, a simple and low cost gate driver for high voltage thyristor diode switches is investigated. This gate driver can operate several high voltage thyristor diode switches at the same time.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.2133-2135
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• 1998

Many semiconductive switches are operated in series for high voltage operation. The same number of gate drivers are needed to control all the switches, hence, the drivers cause high cost and system complexity. In this study, a simple and low cost gate driver for high voltage thyristor-diode switches is investigated. This gate driver can operate several high voltage thyristor-diode switches at the same time.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.82-88
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• 1996

A simpel formular is proposed for the analysis of gate delay of CMOS gate in the low V$_{GS}-V_{TH}$ scaling. The effects of magnitude of V$_{GS}-V_{TH}$ on gate delay can be readily found through the formula so that it can be used ot design the device parameters in the low V$_{DD}$ CMOS circuits. The measured sresutls confirm the usability of the proposed formula and quantifies the improtance of V$_{TH}$ effects on gate delay under low voltae operation. Applying the formula to the prototype NMOSFET devices representing the five generations of technology, the impacts of the V$_{GS}-V_{TH}$ on the various aspects of the circuit and device characteristics are investigated in a consistent manner.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.6
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• pp.429-436
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• 2021

The design of a gate driver power supply for a three-phase inverter using a silicon carbide (SiC) MOSFET. The requirements for the power supply circuit of the gate driver for the SiC MOSFET are investigated, and a flyback converter using multiple transformers is used to make the four isolated power supplies. The proposed method has the advantage of easily constructing the power supply circuit in a limited space as compared with a multi-output flyback converter using a single core. The power supply circuit for the three-phase SiC MOSFET inverter for driving an AC motor is designed and implemented. The operation and validity of the implemented circuit are verified through simulations and experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.6
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• pp.1027-1034
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• 2017

In this paper, we propose a new function embedding method that can measure mathematical projections of probability amplitude, probability, average expectation and matrix elements of stationary-state unit matrix at all control operation points of quantum gates. The function embedding method in this paper is to embed orthogonal normalization condition of probability amplitude for each control operating point into a binary scalar operator by using Dirac symbol and Kronecker delta symbol. Such a function embedding method is a very effective means of controlling the arithmetic power function of a unitary gate in a unitary transformation which expresses a quantum gate function as a tensor product of a single quantum. We present the results of evolutionary operation and projective measurement when we apply the proposed function embedding method to the ternary 2-qutrit cNOT gate and compare it with the existing methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2183-2188
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• 2014

This paper has analyzed threshold voltage movement for channel doping concentration of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is generally fabricated with low doping channel and fully depleted under operation. Since impurity scattering is lessened, asymmetric DGMOSFET has the adventage that high speed operation is possible. The threshold voltage movement, one of short channel effects necessarily occurred in fine devices, is investigated for the change of channel doping concentration in asymmetric DGMOSFET. The analytical potential distribution of series form is derived from Possion's equation to obtain threshold voltage. The movement of threshold voltage is investigated for channel doping concentration with parameters of channel length, channel thickness, oxide thickness, and doping profiles. As a result, threshold voltage increases with increase of doping concentration, and that decreases with decrease of channel length. Threshold voltage increases with decrease of channel thickness and bottom gate voltage. Lastly threshold voltage increases with decrease of oxide thickness.

• 전기의세계
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• v.22 no.2
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• pp.70-74
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• 1973

This paper dealt with circuit modeling of SCR and gate turn-off SCR by using complementary symmetrical tansistor circuit, which is modified circuit of input current dependent, current stable negative resitance circuit. Operation of this circuit is estimated and analyzed, with which compared with conventional SCR modeling circuit. Also operation and the design procedures are checked by experiments.

• Journal of Environmental Science International
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• v.18 no.9
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• pp.971-981
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• 2009

An objective of this study is as follows: 1) performing sensitivity analysis and parameter estimation of RMA2 and RMA4 models for the West-Nakdong River, 2) drawing up alternatives of gates-operation for water-quality enhancement, and 3) quantitative evaluation of methodology of 'flow-restoration by gates-operation' among 'Comprehensive Plan Improving Water-Quality in the West-Nakdong River(WNR)' with the target water-quality(BOD at Nakbon-N point: below 4.3 mg/L). The parameters for the RMA2 (depth-averaged two-dimensional flow model) and RMA4 (depth-averaged two-dimensional water-quality model) were determined by sensitivity analysis. Result of parameter estimation for RMA2 and RMA4 models is $1,000\;Pa{\cdot}s$ of the eddy viscosity, 20 of the Peclet number, 0.025 of the Manning coefficient, and $1.0\;m^2/s$ of the diffusion coefficient. We have evaluated the effects of water-quality enhancement of the selected alternatives by numerical simulation technique with the models under the steady-state flow condition and the time-variant transport condition. Because of no-resuspension from river bottom and considering BOD as conservative matter, these simulation results slightly differ from real phenomena. In the case of $50\;m^3/s$ of Daejeo-gate inflow, two-dimensional flow pn results result represents that small velocity occurs in the Pyungkang Stream and no flow in the Maekdo River. In the WNR, there occurs the most rapid flow near timhae-bridge. In the WNR, changes of water-quality for the four selected simulation cases(6, 10, 30, $50\;m^3/s$ of the Daejeo-gate inflow) were predicted. Since the Daejeo-Gate and the Noksan-Gate can be opened up to 7 days, it would be found that sustainable inflow of $30\;m^3/s$ at the Daejeo-gate makes BOD in the WNR to be under the target of water-quality.