DOI QR코드

DOI QR Code

A Continuous Regional Current-Voltage Model for Short-channel Double-gate MOSFETs

  • Zhu, Zhaomin (Key Laboratory of Advanced Process Control for Light Industry (Ministry of Education),Department of Electronic Engineering, Jiangnan University) ;
  • Yan, Dawei (Key Laboratory of Advanced Process Control for Light Industry (Ministry of Education),Department of Electronic Engineering, Jiangnan University) ;
  • Xu, Guoqing (Key Laboratory of Advanced Process Control for Light Industry (Ministry of Education),Department of Electronic Engineering, Jiangnan University) ;
  • Peng, Yong (Key Laboratory of Advanced Process Control for Light Industry (Ministry of Education),Department of Electronic Engineering, Jiangnan University) ;
  • Gu, Xiaofeng (Key Laboratory of Advanced Process Control for Light Industry (Ministry of Education),Department of Electronic Engineering, Jiangnan University)
  • Received : 2012.10.15
  • Accepted : 2013.02.27
  • Published : 2013.06.30

Abstract

A continuous, explicit drain-current equation for short-channel double-gate (DG) MOSFETs has been derived based on the explicit surface potential equation. The model is physically derived from Poisson's equation in each region of operation and adopted in the unified regional approach. The proposed model has been verified with numerical solutions, physically scalable with channel length and gate/oxide materials as well as oxide/channel thicknesses.

Keywords

References

  1. J. P. Colinge, Solid-State Electron., vol. 48, pp. 897-905, 2004. https://doi.org/10.1016/j.sse.2003.12.020
  2. Q. Chen, K. A. Bowman, E. M. Harrell, and J. D. Meindl, "Double jeopardy in the nanoscale court," IEEE Circuits Devices Mag., vol. 19, no.1, pp. 28- 34, Jan. 2003.
  3. K. Kim and J. G. Fossum, IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 294-299, Feb. 2001. https://doi.org/10.1109/16.902730
  4. K. Suzuki and T. Sugii, IEEE Trans. Electron Devices, vol. 42, no. 11, pp. 1940-1948, Nov. 1995. https://doi.org/10.1109/16.469401
  5. H. R. Farrah and R. F. Steinberg, "Analysis of double-gate thin-film transistor," IEEE Trans. Electron Devices, vol. ED-14, no. 2, pp. 69-74, Feb. 1967.
  6. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance," IEEE Electron Device Lett., vol. EDL-8, no. 9, pp. 410- 412, Sept. 1987.
  7. K. K. Young, "Analysis of conduction in fully depleted SOI MOSFET's," IEEE Trans. Electron Devices, vol. 36, no. 3, pp. 504-506, Mar. 1989. https://doi.org/10.1109/16.19960
  8. K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, "Scaling theory for double-gate SOI MOSFET's," Electron Devices, IEEE Transactions on, vol. 40, no. 12, pp. 2326-2329, Dec. 1993. https://doi.org/10.1109/16.249482
  9. P. Francis, A. Terao, D. Flandre, and F. Van de Wiele, "Modeling of ultrathin double-gate nMOS/SOI transistors," IEEE Trans. Electron Devices, vol. 41, no. 5, pp. 715-720, May 1994. https://doi.org/10.1109/16.285022
  10. J. W. Sleight and R. Rios, "A continuous compact MOSFET model for fully- and partially-depleted SOI devices," IEEE Trans. Electron Devices, vol. 45, no. 4, pp. 821-825, Apr. 1998. https://doi.org/10.1109/16.662786
  11. Y. Taur, "Analytic solutions of charge and capacitance in symmetric and asymmetric doublegate MOSFETs," IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2861-2869, Dec. 2001. https://doi.org/10.1109/16.974719
  12. X. Shi and M. Wong, "Analytical solutions to the one-dimensional oxide-silicon-oxide system," IEEE Trans. Electron Devices, vol. 50, no. 8, pp. 1793-1800, Aug. 2003. https://doi.org/10.1109/TED.2003.815138
  13. A. Ortiz-Conde, and F. J. Garcia-Sanchez, and S. Malobabic, "Analytic solution of the channel potential in undoped symmetric dual-gate MOSFETs," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1669-1672, Jul. 2005. https://doi.org/10.1109/TED.2005.850629
  14. Y. S. Yu, S. H. Kim, S. W. Hwang, and D. Ahn, "All-analytic surface potential model for SOI MOSFETs," IEE Proc.-Circuits Devices Systems, vol. 152, no. 2, pp. 183-188, 2005. https://doi.org/10.1049/ip-cds:20041110
  15. A. Ortiz-Conde, R. Herrera, P. E. Schmidt, F. J. Garcia Sanchez, and J. Andrian, "Long-channel silicon-on-insulator MOSFET theory," Solid-State Electron., vol. 35, pp. 1291-1298, Sept. 1992. https://doi.org/10.1016/0038-1101(92)90164-8
  16. Y. Taur, IEEE Electron Device Lett., vol. 21, pp. 245-247, May 2000. https://doi.org/10.1109/55.841310
  17. J. He, X. Xi, C.-H. Lin, M. Chan, A. Niknejad, and C. Hu, Proc. NSTI WCM-Nanotech 2004, Boston, vol. 2, pp. 124-127, 2004.
  18. S. Malobabic, A. Ortiz-Conde, F. J. G. Sanchez, Proc. 5th IEEE International Carrcas Conference on Devices, Circuits and Systems, Dominican Republic, pp. 19-25, Nov, 2004.
  19. X. Shi and M. Wong, IEEE Trans. Electron Devices, vol. 50, pp. 1793-1800, Aug. 2003. https://doi.org/10.1109/TED.2003.815138
  20. A. Ortiz-Conde, F. J. Garcia Sanchez, M.Guzman, Solid-State Electron., vol. 47, pp. 2067-2074, 2003. https://doi.org/10.1016/S0038-1101(03)00242-9
  21. Taur et. al., "A Continuous, Analytic Drain-Current Model for DG MOSFETs," IEEE ELECTRON DEVICE LETTERS, Vol. 25, No. 2, FEBRUARY 2004
  22. Z. Zhu, X. Zhou, S. C. Rustagi, G. H. See, S. Lin, G. Zhu, C. Wei, and J. Zhang, "Analytic and explicit current model of undoped double-gate MOSFETs," Electron. Lett., Vol. 43, No. 25, pp. 1464-1466, Dec. 2007. https://doi.org/10.1049/el:20072682
  23. Zhaomin Zhu, Xing Zhou, Karthik Chandrasekaran, Subhash C. Rustagi, and Gui Hui See, "Explicit Compact Surface-potential and Drain-Current Models for Generic Asymmetric Double-gate Metal- Oxide-Semiconductor Field-Effect Transistors", Japanese Journal of Applied Physics, Vol. 46, No. 4B, 2007, pp 2067-2072 https://doi.org/10.1143/JJAP.46.2067
  24. R. M. Corless, G. H. Gonnet, D. E. G. Hare, and D. J. Jeffrey, "Lambert's W Function in Maple," Technical Report, Dept. of Applied Math., Univ. of Western Ontario, Canada.
  25. X. Zhou, S. B. Chiah, K. Chandrasekaran, G. H. See, W. Shangguan, S. M. Pandey, M. Cheng, S. Chu, and L.-C. Hsia, Proc. NSTI Nanotech 2005, Anaheim, May, 2005, vol. WCM, pp. 25-30.
  26. Xiaoping Liang, and Yuan Taur, "A 2-D Analytical Solution for SCEs in DG MOSFETs," IEEE Trans. Electron Devices, Vol. 51, pp. 1385-1391, Aug. 2004. https://doi.org/10.1109/TED.2004.832707
  27. Christian C. Enz, and Eric A. Vittoz, "Chargebased MOS Transistor Modeling: The EKV Model for Low-Power and RF IC Design", John Wiley & Sons, Ltd, 2006, pp. 59