• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.471-477
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• 2014

In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and far-field measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• Proceedings of the Acoustical Society of Korea Conference
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• 1993.06a
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• pp.117-120
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• 1993

In this paper, we explore the possibility of URAN(Universally Reconstructable Artificial Neural-network) VLSI chip for speech recognition. URAN, a newly developed analog-digital hybrid neural chip, is discussed in respects to its input, output, and weight accuracy and their relations to its performance on speaker independent digit recognition. Multi-layer perceptron(MLP) nets including a large frame input layer are used to recognize a digit syllable at a forward retrieval. The simulation results using the full and limited floating precision computations for the input, output, and weight variables of the network give the comparable classification performance. An MLP with piecewise linear hidden and output units is also trained successfully using low accuracy computation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.34-41
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• 1998

In this paper, I designed a P1394 serial bus chip as new bus interface architecture which can transmit the multimedia data at the rate of 400 Mbps and guarantee necessary bandwidth. because multimedia data become meaningless data after appropriate time, it is necessary to transfer multimedia data in real time, P1394 serial bus chip designed in this paper support isochronous transfer mode to solve this problem. Also, designed P1394 serial bus chip can transfer high quality video data or high quality audio data because it support the speed of 400 Mbps. While user must set device ID manually in previous interface such as SCSI, device ID is automatically determined if user connect each node with designed P1394 serial bus cable and power on. To design this chip, I verified the behavioral of the entrire system and synthesized layout. Also, I did layout the analog blocks and blocks which must be optimized in full custom.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1045-1054
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• 2002

We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.175-183
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• 2014

In this paper, we present the design and implementation of real-time sound localization based on $0.13{\mu}m$ CMOS process. Time delay of arrival (TDOA) estimation was used to obtain the direction of the sound signal. The sound localization chip consists of four modules: data buffering, short-term energy calculation, cross correlation, and azimuth calculation. Our chip achieved real-time processing speed with full range ($360^{\circ}$) using three microphones. Additionally, we developed a dedicated sound localization circuit (DSLC) system for measuring the accuracy of the sound localization chip. The DSLC system revealed that our chip gave reasonably accurate results in an experiment that was carried out in a noisy and reverberant environment. In addition, the performance of our chip was compared with those of other chip designs.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.165-171
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• 1996

A noncoherent full-digital PN(pseudo noise) code acquisition/tracking loop has been presetned and implemented in FPGA for the CDMA band-limited direct-sequence spread-spectrum (DS-SS) signals. It employs a simple decimator to control of local PN code phase to lower the hardware cost, and a second order loop to enable the more accurate tracking. The proposed acquisition/tracking loop has been designed in RTL-level VHDL, synthesized into logic gates using the design analyzer of synopsys software, implemented in an ALTERA FPGA chip, and tested. The number of logic gates used in the implemented FPGA chip is around 7000. The functionality has been verified using a PC interface circuitry and a logic analyzer.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Journal of the Korean Vacuum Society
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• v.12 no.4
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• pp.235-238
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• 2003

Conventional LED displays use pixels which consist of red, green and blue LEDs of different operation voltages and degradation characteristics. Thus, the circuits are complicated and the display of each color changes independently with the operated time. In order to solve these drawbacks, an LED chip of a short wavelength and an LED lamp with the mixture of red, green, blue fluorescencers and epoxy on the LED chip were studied. The fluorescencers are excited by the light of the LED chip. The LED chip has an active layer of InGaN, a peak wavelength of 408 nm, a FWHM of 13 nm and the CIE index of (0.198, 0.087). White LED lamps were obtained and the CIE index change was observed with the change of the epoxy amount added to the fluorescencers.

• Journal of Information Processing Systems
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• v.3 no.1
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• pp.16-20
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• 2007

This paper describes the development of the sensor interface and driver program for a point of care (POC) device. The proposed pac device comprises an ARM9 embedded processor and eight-channel sensor input to measure various bio-signals. It features a user-friendly interface using a full-color TFT-LCD and touch-screen, and a bluetooth wireless communication module. The proposed device is based on the system on a programmable chip (SOPC). We use Altera's Excalibur device, which has an ARM9 and FPGA area on a chip, as a test bed for the development of interface hardware and driver software.