• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2457-2464
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• 2011

In this paper, a vibration energy harvesting circuit using a piezoelectric device is designed. MPPT(Maximum Power Point Tracking) control function is implemented using the electric power-voltage characteristic of a piezoelectric device to deliver the maximum power to load. The designed MPPT control circuit traces the maximum power point by periodically sampling the open circuit voltage of a full-wave rectifier circuit connected to the piezoelectric device output and delivers the maximum available power to load. The proposed vibration energy harvesting circuit is designed with $0.18{\mu}m$ CMOS process. Simulation results show that the maximum power efficiency of the designed circuit is 91%, and the chip area except pads is $700{\mu}m{\times}730{\mu}m$.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.62-70
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• 1999

This paper introduces a possibility of a low-cost, high-resolution fingerprint sensor chip. The test chip is composed of $64{\times}256$ sensing cells(chip size : $2.7mm{\times}10.8mm$). A new detection circuit of charge sharing is proposed, which eliminates the influences of internal parasitic copacitances. This the reduced sensing-capacitor size enables a high resolution of 600dpi, using even conventional 0.6${\mu}m$ CMOS process. The partial fingerprint image captured therefrom are synthesized into a full fingerprint image with a image synthesis algorithm. The problems and possibilities of image synthesis technique are also analyzed and discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.309-315
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• 2010

A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to the gate leakage current of the OTA input transistor, the feedback pseudo-resistor of the conventional ECG amplifier is moved to input branch between the OP amp summing node and the DC reference voltage. Also, an OTA circuit with a Gm boosting block without reducing the output resistance (Ro) is proposed to maximize the OTA DC gain. The measurements shows the frequency bandwidth from 7 Hz to 480 Hz, the midband gain programmable from 48.7 dB to 59.5 dB, the total harmonic distortion (THD) less than 1.21% with a full voltage swing, and the power consumption of 233 nW in a 0.13 ${\mu}m$ CMOS process at the supply voltage of 0.7 V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.7
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• pp.1581-1588
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• 2010

Most digital cameras use a single image sensor with Color Filter Array(CFA) for the advantage of costs and speed. The various color interpolation(demosaicing) algorithms are researched to reconstruct a full representation of the image. In this paper, we proposed a method of demosaicing about using weighted directional filter for vertical, horizontal, and diagonal direction edge. The method considered the efficiency of hardware resources for hardware implementation. The performance of proposed method was confirmed by comparing the conventional method in experiments using 24 Kodak test images. The proposed method was designed by Verilog HDL and was verified by using Virtex4 FPGA boards and CMOS Image Sensor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.175-183
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• 2014

In this paper, we present the design and implementation of real-time sound localization based on $0.13{\mu}m$ CMOS process. Time delay of arrival (TDOA) estimation was used to obtain the direction of the sound signal. The sound localization chip consists of four modules: data buffering, short-term energy calculation, cross correlation, and azimuth calculation. Our chip achieved real-time processing speed with full range ($360^{\circ}$) using three microphones. Additionally, we developed a dedicated sound localization circuit (DSLC) system for measuring the accuracy of the sound localization chip. The DSLC system revealed that our chip gave reasonably accurate results in an experiment that was carried out in a noisy and reverberant environment. In addition, the performance of our chip was compared with those of other chip designs.

• Journal of IKEEE
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• v.18 no.1
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• pp.37-44
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• 2014

In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier's Bandwidth is 50.8MHz and its phase margin is $59.2^{\circ}C$. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from $-40^{\circ}C$ to $125^{\circ}C$ we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a $1{\mu}F$ output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in $0.35{\mu}m$ CMOS process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.12
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• pp.1301-1307
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• 2004

Reduced pressure chemical vapor deposition(RPCYD) technology has been investigated for the growth of SiGe epitaxial films with two dimensional in-situ doped boron impurities. The two dimensional $\delta$-doped impurities can supply high mobility carriers into the channel of SiGe heterostructure MOSFETs(HMOS). Process parameters including substrate temperature, flow rate of dopant gas, and structure of epitaxial layers presented significant influence on the shape of two dimensional dopant distribution. Weak bonds of germanium hydrides could promote high incorporation efficiency of boron atoms on film surface. Meanwhile the negligible diffusion coefficient in SiGe prohibits the dispersion of boron atoms: that is, very sharp, well defined two-dimensional doping could be obtained within a few atomic layers. Peak concentration and full-width-at-half-maximum of boron profiles in SiGe could be achieved in the range of 10$^{18}$ -10$^{20}$ cm$^{-3}$ and below 5 nm, respectively. These experimental results suggest that the present method is particularly suitable for HMOS devices requiring a high-precision channel for superior performance in terms of operation speed and noise levels to the present conventional CMOS technology.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.305-308
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• 2002

An 1.8V 6bit IGSPS ADC for high speed data acquisition is discussed in this paper. This ADC is based on a flash ADC architecture because the flash ADC is the only practical architecture at conversion rates of IGSPS and beyond. A straightforward 6bit full flash A/D converter consists of two resistive ladders with 63 laps, 63 comparators and digital blocks. One important source of errors in flash A/D converter is caused by the capacitive feedthrough of the high frequency input signal to the resistive reference-lauder. Consequently. the voltage at each tap of the ladder network can change its nominal DC value. This means large transistors have a large parasitic capacitance. Therefore, a dual resistive ladder with capacitor is employed to fix the DC value. Each resistive ladder generates 32 clean reference voltages which alternates with each other. And a two-stage amplifier is also used to reduce the effect of the capacitive feedthrough by minimizing the size of MOS connected to reference voltage. The proposed ADC is based on 0.18${\mu}{\textrm}{m}$ 1-poly 6-metal n-well CMOS technology, and it consumes 307㎽ at 1.8V power supply.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• 전자공학회논문지 IE
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• v.49 no.1
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• pp.1-6
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• 2012

For the performance improvement of a time-to-digital converter(TDC), a 2-stage high resolution TDC has been designed by using a 2-stage vernier time amplifier(2-S VTA). The two stage vernier time amplifier which has a gain over 64 of the resolution can enhance the resolution of the whole two stage TDC. Because of using a vernier TDC, the structure is not limited to advanced processes for achieving high resolution. The proposed TDC has been designed in a $0.18{\mu}m$ CMOS process and simulated with a 1.8V supply voltage. The entire input range is 512ps, and the full resolution 0.125ps.