• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.4
• /
• pp.103-109
• /
• 2007

This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. By adopting a top-down approach along with the traditional bottom-up transistor level design in parallel, the design time is greatly shortened, and a co-verification method for both the digital and the analog part is considered. Under this consideration, the SIMULINK modeling reduces simulation time and easily estimates the PLL's performance on the top level. Verilog-a is able to verify the feasibility of each blocks at first hand because it is compatible with transister level circuits. Then, an efficient way of the design is presented by comparing the results of both models.

• Bulletin of the Korean Mathematical Society
• /
• v.57 no.5
• /
• pp.1143-1149
• /
• 2020

Sobolev trace inequalities on nonhomogeneous fractional Sobolev spaces are established.

• Nonlinear Functional Analysis and Applications
• /
• v.28 no.2
• /
• pp.439-448
• /
• 2023

In this article, we are interested in studying the fractional Sadik Transform and a combination of the method of steps that will be applied together to find accurate solutions or approximations to homogeneous and non-homogeneous delayed fractional differential equations with constant-coefficient and possible extension to time-dependent delays. The results show that the process is correct, exact, and easy to do for solving delayed fractional differential equations near the origin. Finally, we provide several examples to illustrate the applicability of this method.

• Bulletin of the Korean Mathematical Society
• /
• v.48 no.2
• /
• pp.353-363
• /
• 2011

Let k $\geq$ 1 be an integer, and let G be a 2-connected graph of order n with n $\geq$ max{7, 4k+1}, and the minimum degree $\delta(G)$ $\geq$ k+1. In this paper, it is proved that G has a fractional k-factor excluding any given edge if G satisfies max{$d_G(x)$, $d_G(y)$} $\geq$ $\frac{n}{2}$ for each pair of nonadjacent vertices x, y of G. Furthermore, it is showed that the result in this paper is best possible in some sense.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.4
• /
• pp.534-542
• /
• 2017

This paper presents a fast locking technique for a fractional-N PLL frequency synthesizer. The technique directly measures $K_{VCO}$ on a chip, computes the VCO's target tuning voltage for a given target frequency, and directly sets the loop filter voltage to the target voltage before the PLL begins the normal closed-loop locking process. The closed-loop lock time is significantly minimized because the initial frequency of the VCO are put very close to the desired final target value. The proposed technique is realized and designed for a 4.3-5.3 GHz fractional-N synthesizer in 65 nm CMOS and successfully verified through extensive simulations. The lock time is less than $12.8{\mu}s$ over the entire tuning range. Simulation verifications demonstrate that the proposed method is very effective in reducing the synthesizer lock time.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.441-442
• /
• 2008

In this paper a Fractional-N frequency synthesizer is designed for UHF RFID readers. It satisfies the ISO/IEC frequency band $(860{\sim}960MHz)$ and is also applicable to mobile RFID readers. It is designed using a $0.18{\mu}$ RF CMOS process. The measured results show that the designed circuit has a phase noise of -103dBc/Hz at 100kHz offset and consumes 9mA from a 1.8V supply. The channel switching time of $10{\mu}s$ over 5MHz transition have been achieved, and the chip size including PADs is $1.8{\times}0.99mm^2$

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.521-522
• /
• 2006

This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. The SIMULINK modeling was built in the frequency-time mixed domain whereas the Verilog-a modeling was built purely in the time domain. The simulated results of the two models were verified to show the same performance within the error tolerance. This top-down design method can provide the readiness for the transistor-level design.

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.890-893
• /
• 2003

In this paper, we have designed the fractional-N frequency synthesizer for bluetooth system using 0.35-um CMOS technology and 3.3-V single power supply. The designed synthesizer consist of phase-frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), frequency divider, and sigma-delta modulator. A dead zone free PFD is used and a modified charge pump having active cascode transistors is used. A Multi-modulus prescaler having CML D flip-flop is used and VCO having a tuning range from 746 MHz to 2.632 GHz at 3.3 V power supply is used. Total power dissipation is 32 mW and phase noise is -118 dBc/Hz at 1 MHz offset.

• Communications of the Korean Mathematical Society
• /
• v.36 no.3
• /
• pp.557-573
• /
• 2021

In this present paper, we consider four integrals and differentials containing the Gauss' hypergeometric ₂F₁(x) function in the kernels, which extend the classical Riemann-Liouville (R-L) and Erdélyi-Kober (E-K) fractional integral and differential operators. Formulas (images) for compositions of such generalized fractional integrals and differential constructions with the n-times product of the generalized modified Bessel function of the second type are established. The results are obtained in terms of the generalized Lauricella function or Srivastava-Daoust hypergeometric function. Equivalent assertions for the Riemann-Liouville (R-L) and Erdélyi-Kober (E-K) fractional integral and differential are also deduced.

• Nonlinear Functional Analysis and Applications
• /
• v.26 no.3
• /
• pp.497-512
• /
• 2021

In this paper, we study the analytical and approximate solutions for a fractional quadratic integral equation involving Katugampola fractional integral operator. The existence and uniqueness results obtained in the given arrangement are not only new but also yield some new particular results corresponding to special values of the parameters 𝜌 and ϑ. The main results are obtained by using Banach fixed point theorem, Picard Method, and Adomian decomposition method. An illustrative example is given to justify the main results.