• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.678-684
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• 2013

This paper describes a low-power baseband circuit for SAW-less LTE-Advanced transmitters. The proposed transmitter baseband circuit consists of a 2nd-order Tow-Thomas type active RC-LPF and a 1st-order passive RC LPF. It can provide a 7 multi-channel cut-off frequencies and wide gain control range of -41 dB ~ 0 dB with a 1-dB step. The proposed 2nd-order active RC-LPF adopts an op-amp in which three other sub-op amps are in parallel connected to reduce DC current for different cutoff frequency. In addition, each sub-op amp adopts both Miller and feed-forward phase compensation method to achieve an UGBW of more than 1-GHz with a small DC power consumption. The proposed baseband circuit is implemented in 65-nm CMOS technology, consuming DC power from 6.3 mW to 24.1 mW from a 1.2V supply voltage for each different cut-off frequency.

• Korean Journal of Optics and Photonics
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• v.23 no.2
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• pp.64-70
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• 2012

We analyzed the changes in electrical and optical characteristics of 1 $mm^2$ multiple-quantum-well (MQW) blue LEDs grown on a c-plane sapphire substrate after a stress test. Experiments were performed by injecting 50 mA current for 200 hours to TO-CAN packaged sample chips. We selected the value of injection current for stress through the junction-temperature measurement by using the forward-voltage characteristics of a diode to maintain a sufficiently low junction temperature during the test. The junction temperature at the selected injection current of 50 mA was 308 K. Experiments were performed under the assumption that the average junction temperature of 308 K did not affect the characteristics of the ohmic contact and the GaN-based materials. Before and after the stress test, we measured and analyzed current-voltage, light-current, light distribution on the LED surface, wavelength spectrum and relative external quantum efficiency (EQE). After the stress test, it was observed experimentally that the optical power and the relative EQE decreased. We theoretically investigated and experimentally proved that these phenomena are due to the increased nonradiative recombination rate caused by the increased defect density.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.10-16
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• 2011

We report on the simulation results of electrical/optical characteristics for nonpolar GaN LED having Mg-doped GaN spacer and quantum barrier, in comparison with those of the typical nonpolar GaN LED. In order to reduce the band-gap energy distortion and conduction-band discontinuity in InGaN/GaN multiple quantum wells(MQWs) of nonpolar GaN LED, and thereby to increase their current-voltage, light output power and emission peak intensity, we applied 6 nm-thick p-type($1{\times}10^{18}\;cm^{-3}$) GaN spacer and GaN QB schemes to the typical nonpolar GaN LED epitaxial structure. As a result, we found that the radiative recombination rate was increased by 23% in MQWs at 20 mA current injection. Also, the forward voltage($V_f$) and the light output power($P_{out}$) were improved by 3.7% and 7%, respectively, for the proposed nonpolar LED epitaxial structure, compared with those of the typical nonpolar GaN LED.

• Journal of the Korean Vacuum Society
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• v.19 no.2
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• pp.134-140
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• 2010

We have investigated the contactless electroreflectance (CER) properties of $In_{0.5}(Ga_{1-x}Al_x)_{0.5}P$/GaAs double heterostructures grown by metal-organic chemical vapour deposition (MOCVD). The CER measurements on the sample were studied as a function of temperature, modulation voltage ($V_{ac}$), and dc bias voltage ($V_{bias}$). Five signals observed at room temperature are related to the GaAs, $In_{0.5}Ga_{0.5}P$, $In_{0.5}(Ga_{0.73}Al_{0.27})_{0.5}P$, $In_{0.5}(Ga_{0.5}Al_{0.5})_{0.5}P$, and $In_{0.5}(Ga_{0.2}Al_{0.8})_{0.5}P$ transitions, respectively. From the temperature dependence of CER spectrum, the Varshni coefficients and broadening parameters were determined and discussed. In addition, we found that the behavior of the CER amplitude for the reverse bias is larger than that of the forward.

• Journal of the Korean Vacuum Society
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• v.6 no.2
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• pp.136-142
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• 1997

An/n-GaAs(100) Schottky barrier diode has been investigated by using electoreflectance(ER). From the observed Franz-Keldysh oscillatins(FKO), the internal electric field(Ei) of the sample is $5.76\times 10^{4}$V/cm at 300 K. As the modulation voltage($V_{ac}$) IS changed, the line shape of ER signal does not change but its amplitude various linerly. For increasing forward and reverse dc bias boltage($V_{bias}$), the amplitude of ER signal decreases. The internal electric field decreased from $19.3\times 10^4\sim4.39\times10^4$V/cm as $V_{bias}$ INCREASES FROM -5.0 V TO 0.6 V. For Au/n-GaAs the valve of built-in voltage($V_{bi}$) determined from the plot of $V_{bias}$ versus $E_i^2$ is 0.70 V. This value agrees with that observed in the plot of $V_{bias}$ versus amplitude of FKO peak. In addition, the carrier concentraion(N) and potential barrier($\Phi$) of the sample at 300 K are found to be about $2.4\times 10^{16}\textrm{cm}^{-3}$ and 0.78 eV, respectively.

• Journal of Sensor Science and Technology
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• v.5 no.3
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• pp.101-108
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• 1996

The silicon $p^{+}-n$ junction diodes were fabricated. The fabricated wafers were treated by single or double annealing steps. Single annealing process was performed by diffusion of either Au or Pt into the wafer under the oxygen or nitrogen ambient at $800{\sim}1010^{\circ}C$. Second annealing step involved additional annealing of the single annealed wafer under the oxygen ambient at $800{\sim}1010^{\circ}C$ for one hour. Electrical characteristics of the diodes were investigated to evaluate the effect of the annealing treatments. In the case of single annealing under nitrogen ambient at $1010^{\circ}C$ for one hour, the amount of leakage current of Pt diffused diode was 75 times larger than that of Au diffused one. The optimum processing condition to achieve high speed silicon $p^{+}-n$ junction diodes from this study was obtained when Pt diffused wafer(treated under the nitrogen ambient at $1010^{\circ}C$ for one hour) was secondly annealed in an oxygen ambient at $800^{\circ}C$ for one hour. The resulting leakage current of two step annealed diodes were remarkably reduced to 1/1100 of the single annealed one. The diode characteristics such as recovery time, breakdown voltage, leakage current, and forward voltage were 4ns, 138V, 1.72nA, and 1V, respectively.

• Journal of Korean Society of Environmental Engineers
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• v.35 no.10
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• pp.749-755
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• 2013

The purposes of this research are to know the optimal gab and electric pressure (voltage) of electrode-plates coated with activated carbon and also to study their arrangement through dust removal efficiency. From the experimental results of attached dust mass at different electrode-plate gab, the frequency of attachment and detachment of dust was more increased as electrode-plate gab was closer. In attached dust mass per unit area of electrode-plate, the farther electrode gab, the more increased. But in total attached dust mass, the closer electrode gab, the more removed. From the experimental results, the optimal electrode arrangement in dust removal chamber was considered that the forward parts of chamber need to be increased the number of electrode-plate, the backward parts to be increased them. The dust attachment have no relation with electric pressure while showing high removal efficiency under condition of 5 kV of voltage and 2 cm of electrode-plates gab.

• Transactions on Electrical and Electronic Materials
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• v.16 no.2
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• pp.86-89
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• 2015

Uniform ZrO₂ nanoballs were synthesized at 700℃ using the inverse replication method through a colloid-imprinted carbon (CIC) template. The structural, dielectric, and conducting properties of the ZrO₂ nanoballs were investigated and compared with those of ZrO₂ film prepared by sol-gel method and powdered ZrO₂ chemical. Both the monoclinic and cubic phases were found in the ZrO₂ balls and film but the ZrO₂ chemical showed a monoclinic phase, where the cubic structure is known to be formed at above 2,300℃. ZrO₂ nanoballs showed the lower dielectric property of k = 21.2 at 1 MHz because the 8-coordinated cubic phase in the ZrO₂ nanoball produced lower polarization than the polarization of the 7-coordinated monoclinic ZrO₂ chemical (k = 23.6). The dielectric stability was maintained in each ZrO₂ ball, film, and chemical under the applied forward and reverse voltage range (−5 to +5 V) at 1 MHz. The ionic conductivities were 7.86 × 10⁻⁸/Ω·cm for ZrO₂ nanoballs, 3.29 × 10⁻⁸/Ω·cm for ZrO₂ chemical, and 6.70 × 10⁻⁵/Ω·cm for the thickness of 1,053 nm ZrO₂ film at room temperature with the electronic contribution being less than 0.006%.