Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A LDPC Decoder for DVB-S2 Standard Supporting Multiple Code Rates

DVB-S2 기반에서 다양한 부호화 율을 지원하는 LCPC 복호기

  • Ryu, Hye-Jin (Division of Electronics and Information Engineering, Chonbuk National University) ;
  • Lee, Jong-Yeol (Division of Electronics and Information Engineering, Chonbuk National University)
  • 류혜진 (전북대학교 전자정보공학부) ;
  • 이종열 (전북대학교 전자정보공학부)
  • Published : 2008.02.25
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Abstract

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

디지털 비디오 방송표준(DVB-S2)은 순방향 에러 코딩방법으로 BCH와 LDPC을 연결한 시스템을 내부코딩으로 사용한다. DVB-S2에서 LDPC 코드는 11개의 서로 다른 부호화 율을 정의하고 있기 때문에, DVB-S2 LDPC 복호기는 다양한 부호화 율을 지원해야 한다. 11개의 부호화 율 중에서 7가지(3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10)는 균일한 부호화 율이고, 나머지 4가지(1/4, 1/3, 2/5, 1/2)는 비균일 부호화 율이다. 본 논문에서는 균일한 LDPC 코드를 위한 유연한 복호기를 제시한다. 제안된 복호기는 칩의 면적, 메모리의 효율, 처리속도 등에서 많은 장점을 갖는 반 병렬 복호 구조와 변수노드와 체크노드의 내부 연결선을 줄이고 다양한 부호화 율을 지원할 수 있도록 Benes 네트워크를 결합하여 블록크기가 64,800까지 사용가능하도록 설계하였다. 제안하는 복호기는 200MHz에서 193.2MbPs의 처리속도를 갖으며, 면적은 $16.261m^2$이고, 전력은 공급전압이 1.5V에서 198mW의 소모를 보인다.

Keywords

References

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