• Journal of Information Processing Systems
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• v.8 no.1
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• pp.133-144
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• 2012

In order to make cognitive radio systems a practical technology to be deployed in real-world scenarios, the core Software Defined Radio (SDR) systems must meet the stringent requirements of the target application, especially in terms of performance and energy consumption for mobile platforms. In this paper we present a feasibility study of hardware acceleration as an energy-efficient implementation for SDR. We identified the amplifier function from the Software Communication Architecture (SCA) for hardware acceleration since it is one of the functions called for most frequently and it requires intensive floating-point computation. Then, we used the Virtex5 Field-Programmable Gate Array (FPGA) to perform a comparison between compiler floating-point support and the on-chip floating-point support. By enabling the on-chip floating-point unit (FPU), we obtained as high as a 2X speedup and 50% of the overall energy reduction. We achieved this with an increase of the power consumption by no more than 0.68%. This demonstrates the feasibility of the proposed approach.

• The Journal of the Society of Korean Medicine Diagnostics
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• v.25 no.1
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• pp.1-71
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• 2021

Objectives In order to reinterpret the meaning of Inch-Bar-Cubit used by pulse diagnosis, this study investigates floating pulses of lung and heart in the Inch area, middle pulse of spleen and livers in the Bar area, and deep pulse of kidney and life gate in the Cubit area. However, some suggested that the meaning of Inch-Bar-Cubit should be interpreted in the same way as floating-middle-deep. Methods In this study, the contents of Inch-Bar-Cubit assignment of pulse diagnosis proposed by Dongeuibogam and Medical Scientist were investigated along with the existing investigation of pulse diagnosis, and their interpretation was investigated. Result and conclusion The assignment of books in Pulse diagnosis can be applied by replacing them with floating-middle-deep instead of Inch-Bar-Cubit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.53-58
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• 2006

A Vertex Shader is designed to show more 3D graphics expressions, and to increase flexibility of the fixed function T&L (Transform and Lighting) engine. Design of this Shader is based on Vertex Shader 1.1 of DirectX 8.1 and OpenGL ARB. The Vertex Shader consists of four floating point ALUs for vectors operation. The previous 32bits floating point data type is replaced to 24bits floating point data type in order to design the Vertex Shader that consume low-power and occupy small area. A Xilinx Virtex2 300M gate module is used to verify behaviour of the core. The result of Synopsys synthesis shows that the proposed Vertex Shader performs 115MHz speed at the TSMC 0.13um process and it can operate as the rate of 12.5M Polygons/sec. It shows the complexity of 110,000 gates in the same process.

• Journal of Adhesion and Interface
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• v.23 no.2
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• pp.53-58
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• 2022

Here, the surface characteristics of the dielectric were controlled by introducing the self-assembled monolayers (SAMs) as the intermediate layers on the surface of the AlOx dielectric, and the electrical performances of the organic charge modulated transistor (OCMFET) were significantly improved. The organic intermediate layer was applied to control the surface energy of the AlOx gate dielectric acting as a capacitor plate between the control gate (CG) and the floating gate (FG). By applying the intermediate layers on the gate dielectric surface, and the field-effect mobility (μ_OCMFET) of the OCMFET devices could be efficiently controlled. We used the four kinds of SAM materials, octadecylphosphonic acid (ODPA), butylphosphonic acid (BPA), (3-bromopropyl)phosphonic acid (BPPA), and (3-aminopropyl)phosphonic acid (APPA), and each μ_OCMFET was measured at 0.73, 0.41, 0.34, and 0.15 cm2V-1s-1, respectively. The results could be suggested that the characteristics of each organic SAM intermediate layer, such as the length of the alkyl chain and the type of functionalized end-group, can control the electrical performances of OCMFET devices and be supported to find the optimized fabrication conditions, as an efficient sensing platform device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.7
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• pp.601-604
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• 2006

In this paper, we propose the single poly-Si Flash EEPROM device with a new structure which does not need the high voltage switching circuits. The device was designed, fabricated and characterized. From the measurement results, it was found that the program, the erase and the read operations worked properly. The threshold voltage was 3.1 V after the program in which the control gate and the drain were biased with 12 V and 7 V for $100{\mu}S$, respectively. And it was 0.4 V after the erase in which the control gate was grounded and the drain were biased with 11 V for $200{\mu}S$. On the other hand, it was found that the program and the erase speeds were significantly dependent on the capacitive coupling ratio between the control gate and the floating gate. The larger the capacitive coupling ratio, the higher the speeds, but the target the area per cell. The optimum structure of the cell should be chosen with the consideration of the trade-offs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.2
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• pp.1-6
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• 1983

The reduction of threshold voltage and punchthrough voltage of short channel MOS transistors has been measured experimentally with silicon gate NMOS transistors. The effects of the gate oxide thickness and substrate doping concentration on the threshold voltage and punch-through voltage have also been measured with sample devices with boron implantation and gate oxide thickness of 50 nm and 70 nm. Hot electron emission has been measured by floating gate method for the samples with 3 ${\mu}{\textrm}{m}$ channel length. It has been concluded from this measurement that hot electron emission is not significant for the channel length of 3${\mu}{\textrm}{m}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.401-406
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• 2005

Two dimensional MEDICI simulator is used to study the electrical characteristics of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics with the variations of p-base impurity concentrations and current flow. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have tile better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer u-base structure under the floating N+ emitter indicates to have the better characteristics of latch-up current and breakover voltage in spite of the same turn-off characteristics.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.35-39
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• 2011

An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.325-328
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• 2002

In this paper. we propose a floating resistor with positive and negative resistance operating at lower supply voltages. The circuit uses only two transistors between the supply voltages. which enable to operate it at low supply voltages. Moreover. the circuit uses fewer number of transistors compared to the reported work. The gate terminal is used in this circuit for the current addition/subraction at the terminals of resistor. The characteristic of the proposed circuit is verified using HSPICE for the power supply +/-1.5V.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.165-168
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• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.