• 전력전자학회논문지
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• 제13권2호
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• pp.135-144
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• 2008

일반적으로 Intelligent power module (IPM)의 상부 스위치 구동을 위한 플로팅 전원 공급 방법으로 부트스트랩 회로가 많이 사용되고 있다. 부트스트랩 회로는 구성이 간단하고 집적화가 가능하다는 장점이 있으나 몇 가지 문제점을 가지고 있다. 상부 스위치 게이트 드라이버 회로에 전원을 공급하기 위해 매 주기마다 충분한 에너지를 충전할 수 있는 시간이 요구되며, 충전된 에너지는 한정적이므로 스위치 턴 온 (turn-on)시간의 제한을 갖게 된다. 그리고 주파수가 낮아질수록 부트스트랩 커패시터 용량이 증가하여 집적화에 장애요인이 된다. 이러한 단점은 전하 펌프 회로를 사용함으로써 보완될 수 있다. 본 논문에서는 IPM의 플로팅 전원 공급 방법으로 전하 펌프 회로를 적용하여 분석하였으며, 이러한 분석을 기반으로 전하 펌프 회로의 설계 방법을 제안하였다. 분석과 제안된 설계 방법의 타당성을 검증하기 위하여 시뮬레이션과 실험을 수행하였으며, 제시된 결과는 제안된 설계 방법의 유용성을 입증하였다.

• 한국전기전자재료학회논문지
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• 제18권12호
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• pp.1069-1074
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• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.120-121
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• 2007

Nano-floating gate memory (NFGM) devices were fabricated by using the low temperature poly-Si thin films crystallized by ELA and the $In_2O_3$ nano-particles embedded in polyimide layers as charge storage. Memory effect due to the charging effects of $In_2O_3$ nano-particles in polyimide layer was observed from the TFT NFGM. The post-annealing in 3% diluted hydrogen $(H_2/N_2)$ ambient improved the retention characteristics of $In_2O_3$ nano-particles embedded poly-Si TFT NFGM by reducing the interfacial states as well as grain boundary trapping states.

• 산업기술연구
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• 제27권B호
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• pp.15-20
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• 2007

This paper presents the new design method for the gate driver circuit of the floating MOSFET by using the pulse transformer. Each parameters of the proposed circuit are delivered by the numerical calculation method. By considering inner characteristics of MOSFET, the gate driver makes to increase the efficiency of the power conversion and decrease operating heat. Computer simulations and to experimental results for a Buck Converter are presented in order to validate the proposed method.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.118-118
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• 2011

The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......

• 한국수자원학회논문집
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• 제51권5호
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• pp.405-415
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• 2018

연직수문의 방류량 계산에 필요한 수리학적 변수는 유량계수, 수문개방고, 상류수심이다. 자동수문의 수문개방고는 나머지 변수에도 영향을 미치기 때문에, 운영 중 수문개방고의 거동을 예측하는 것은 정밀한 수문설계를 위해 매우 중요하다. 본 연구에서는 부력식 연직수문 모형을 대상으로 부력이론으로 계산한 수문개방고와 실험에서 방류 중에 측정한 값과의 관계로 부터, 임의의 상류수심에서 수문개방고를 예측할 수 있는 무차원 관계식을 도출하였다. 측정값이 계산 값과 차이가 나는 것은 동수압 하중에 의한 영향임을 압력계수를 이용하여 검증하였다. 유량계수는 수문개방율과의 무차원 관계식을 도출하였다. 도출된 관계식들을 홍수추적에 적용한 결과, 수문설계 시에는 동수압 하중으로 인한 수문개방 억제 효과를 충분히 고려하여야 하는 것으로 판단되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.647-648
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• 2006

This paper presents the design results of peripheral circuits of non-volatile memory of nano floating gate cells. The designed peripheral circuits included command decoder, decoders, sense amplifiers and oscillator, which are targeted with 0.35um technology EEPROM process for operating test and reliable test. The simulation results show each operation and test mode of output voltage for word line, bit line, well and operating of sense amplifier.

• 한국전기전자재료학회논문지
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• 제24권4호
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• pp.325-327
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• 2011

In this paper, nonvolatile nano-floating gate memory devices are fabricated with ZnO nanowires and Al nanoparticles on a $SiO_2/Si$ substrate. Al nanoparticles used as floating gate nodes are formed by the sputtering method. The fabricated device exhibits a threshold voltage shift of -1.5 V. In addition, we investigate the endurance and retention characteristics of the nano-floating gate memory device.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.157-163
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• 2002

A new flash EEPROM device with p^＋ poly-Si control gate and n^＋ poly-Si floating side gate was fabricated and characterized. The n^＋ poly-Si gate is formed on both sides of the p^＋ poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.342-344
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• 2005

We have simulated a symmetric dual-gate TFT which has triple floating n+ channel to improve the on-current of the dual-gate TFT. We achieved a low hole concentration at the source and channel junction causes the improvement the potential barrier so that we observed the reduction of the kink-effect. In this paper, we observed the reduction of the kink-effect compared with the conventional single-gate TFT and the improvement of the on-current compared with the conventional dual-gate TFT.