• Title/Summary/Keyword: Floating Gate

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Effects of source bias on the programming characteristics of submicron EPROM/Flash EEPROM (Submicron EPROM/flash EEPROM의 프로그램 특성에 대한 소오스 바이어스의 영향)

  • 박근숙;이재호;박근형
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.3
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    • pp.107-116
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    • 1996
  • Recently, the flash memory has been abstracting great attention in the semiconductor market in the world because of its potential applications as mass storage devices. One of the most significant barriers to the scalling-down of the stacked-gate devices such as EPROM's and flash EEPROM's is the large subthreshold leakage in the unselected cells connected with the bit line of a selected cell in the array during programming. The large subthreshold leakge is majorly due to the capacitive coupling between the floating gates of the unselectd cells and the bit line of selected cell. In this paper, a new programming method to redcue significantly the drain turn-on leakage in the unselected cells during programming has been studied, where a little positive voltage (0.25-0.75V) is applied to the soruce during programming unlike the conventional programming method in which the source is grounded. The resutls of the PISCES simulations and the electrical measurements for the standard EPROM with 0.35.mu.m effective channel length and 1.0.mu.m effective channel width show that the subthreshold leakage in the unselectd cells is significantly large when the source is grounded, whereas it is negligibly small when the source is biased ot a little positive voltage during programming. On the other hadn, the positive bias on the source is found to have little effects on the programming speed of the EPROM.

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Sensitivity Alterable Biosensor Based on Gated Lateral BJT for CRP Detection

  • Yuan, Heng;Kang, Byoung-Ho;Lee, Jae-Sung;Jeong, Hyun-Min;Yeom, Se-Hyuk;Kim, Kyu-Jin;Kwon, Dae-Hyuk;Kang, Shin-Won
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.1
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    • pp.1-7
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    • 2013
  • In this paper, a biosensor based on a gated lateral bipolar junction transistor (BJT) is proposed. The gated lateral BJT can function as both a metal-oxide-semiconductor field-effect transistor (MOSFET) and a BJT. By using the self-assembled monolayer (SAM) method, the C-reactive protein antibodies were immobilized on the floating gate of the device as the sensing membrane. Through the experiments, the characteristics of the biosensor were analyzed in this study. According to the results, it is indicated that the gated lateral BJT device can be successfully applied as a biosensor. Additionally, we found that the sensitivity of the gated lateral BJT can be varied by adjusting the emitter (source) bias.

An implementation of a unified ALU in multi-core GPGPU based on SIMT architecture (SIMT 구조 기반 멀티코어 GPGPU의 통합 ALU 설계)

  • Kyung, Gyu-taek;Kwak, Jae-Chang;Lee, Kwang-yeob
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.540-543
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    • 2013
  • This paper describes an implementation of a unified ALU on multi-core GPGPU based on SIMT architecture. Our unified ALU can operate conditional branch instructions, data movement instructions, integer arithmetic instructions and floating-point arithmetic instructions. Since multi-core GPGPU contains a lot of ALU for parallel processing of various types, the main point of this paper is to design the minimum size ALU by unifying similar processing of each operations on circit level. All instrunctions were tested by making a test program. And we compare this results with results of CPU operations to verify our ALU. Our unified ALU's gate size is approximately 20,000 and the maximum operation frequency is 430MHz.

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차세대 비 휘발성 메모리 적용을 위한 Staggered tunnel barrier ($Si_3N_4$/HfAlO) 에 대한 전기적 특성 평가

  • Yu, Hui-Uk;Park, Gun-Ho;Nam, Gi-Hyeon;Jeong, Hong-Bae;Jo, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.219-219
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    • 2010
  • 기존의 플로팅 타입의 메모리는 소자의 소형화에 따른 인접 셀 간의 커플링 현상과 전계에 따른 누설전류의 증가 등과 같은 문제가 발생한다. 이에 대한 해결책으로서 전하 저장 층을 폴리실리콘에서 유전체를 사용하는 SONOS 형태의 메모리와 NFGM (Nano-Floating Gate Memory)연구가 되고 있다. 그러나 높은 구동 전압, 느린 쓰기/지우기 속도 그리고 10년의 전하보존에 대한 리텐션 특성을 만족을 시키지 못하는 문제가 있다. 이러한 문제를 해결 하고자 터널베리어를 엔지니어링 하는 TBM (Tunnel Barrier Engineering Memory) 기술에 대한 연구가 활발히 진행 중이다. TBM 기술은 터널 층을 매우 얇은 다층의 유전체를 사용하여 전계에 따른 터널베리어의 민감도를 증가시킴으로써 빠른 쓰기/지우기 동작이 가능하며, 10년의 전하 보존 특성을 만족 시킬 수 있는 차세대 비휘발성 메모리 기술이다. 또한 고유전율 물질을 터널층으로 이용하면 메모리 특성을 향상 시킬 수가 있다. 일반적으로 TBM 기술에는 VARIOT 구조와 CRESTED 구조로 나눠지는데 본 연구에서는 두 구조의 장점을 가지는 Staggered tunnel barrier 구조를 $Si_3N_4$와 HfAlO을 이용하여 디자인 하였다. 이때 HfO2와 Al2O3의 조성비는 3:1의 조성을 갖는다. $Si_3N_4$와 HfAlO을 각각 3 nm로 적층하여 리세스(Recess) 구조의 트랜지스터를 제작하여 차세대 비휘발성 메모리로써의 가능성을 알아보았다.

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Analysis of dynamic downpull force on underflow type floating gate (부력식 수문의 동적 하향력 분석)

  • Lee, Ji Haeng;Han, Il Yeong;Choi, Heung Sik
    • Proceedings of the Korea Water Resources Association Conference
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    • 2018.05a
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    • pp.78-78
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    • 2018
  • 자동수문이란 설정된 관리수위 이하에서는 수문이 개방되지 않고, 유량이 증가하여 관리수위 이상이 되면 수문이 개방되어 관리수위까지 방류하게 되면 다시 수문이 닫히게 되어 자동으로 관리수위를 유지한다는 것을 의미한다. 이러한 연직 자동수문의 방류특성이 수동식 연직수문과 다른 점은 유량에 따라서 수문 개방고의 증감과 수문개폐가 자동으로 이루어진다는 것이다. 따라서 자동수문의 운영 중 수문개방고의 거동과 자동개폐 시점을 예측하는 것은 정밀한 수문설계를 위해 매우 중요하다. 수문 개방 시 흐름이 정지되어있다고 가정하면, 정수압 상태의 부력이론에 의한 부력수문의 개방고는 어렵지 않게 계산할 수 있다. 그러나, 흐름이 정지되어 있다가 수문의 하단으로 방류가 시작되면 수문 선단을 포함한 주변에 압력 차이로 인해 동수압 하중이 발생하게 되어 수문에 진동을 유발하고, 수문개방을 억제하는 힘이 발생하여 수문 운영에 큰 영향을 미친다. 본 연구에서는 부력식 수문의 모형실험을 통하여 정수압 상태의 부력이론에 의한 수문 개방율과 측정에 의한 수문 개방율을 비교하였으며, 압력계수를 이용하여 이론과 측정 수문 개방고의 차이는 동적하중에 의한 효과임을 확인하였다. 모형실험에서 측정된 자료와 수치모형 ANSYS - Fluent의 사용성을 검증하였고, 부력식 수문의 형상에 따른 동적하중을 분석하였다. 수문 형상비는 0.24~1.09로 설정하였고, 분석결과 부력식 수문은 수문 개방율이 커짐에 따라 압력계수는 감소하는 경향을 보였으며, 동적하중은 증가하는 경향을 보였다. 또한, 부력식 수문의 형상비에 따라서는 형상비가 증가함에 따라 동적하중이 감소하는 관계를 확인하였다.

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Implementation and characterization of flash-based hardware security primitives for cryptographic key generation

  • Mi-Kyung Oh;Sangjae Lee;Yousung Kang;Dooho Choi
    • ETRI Journal
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    • v.45 no.2
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    • pp.346-357
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    • 2023
  • Hardware security primitives, also known as physical unclonable functions (PUFs), perform innovative roles to extract the randomness unique to specific hardware. This paper proposes a novel hardware security primitive using a commercial off-the-shelf flash memory chip that is an intrinsic part of most commercial Internet of Things (IoT) devices. First, we define a hardware security source model to describe a hardware-based fixed random bit generator for use in security applications, such as cryptographic key generation. Then, we propose a hardware security primitive with flash memory by exploiting the variability of tunneling electrons in the floating gate. In accordance with the requirements for robustness against the environment, timing variations, and random errors, we developed an adaptive extraction algorithm for the flash PUF. Experimental results show that the proposed flash PUF successfully generates a fixed random response, where the uniqueness is 49.1%, steadiness is 3.8%, uniformity is 50.2%, and min-entropy per bit is 0.87. Thus, our approach can be applied to security applications with reliability and satisfy high-entropy requirements, such as cryptographic key generation for IoT devices.

Design of an 8-Bit eFuse One-Time Programmable Memory IP Using an External Voltage (외부프로그램 전압을 이용한 8비트 eFuse OTP IP 설계)

  • Cho, Gyu-Sam;Jin, Mei-Ying;Kang, Min-Cheol;Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.1
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    • pp.183-190
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    • 2010
  • We propose an eFuse one-time programmable (OTP) memory cell based on a logic process, which is programmable by an external program voltage. For the conventional eFuse OTP memory cell, a program datum is provided with the SL (Source Line) connected to the anode of the eFuse going through a voltage drop of the SL driving circuit. In contrast, the gate of the NMOS program transistor is provided with a program datum and the anode of the eFuse with an external program voltage (FSOURCE) of 3.8V without any voltage drop for the newly proposed eFuse cell. The FSOURCE voltage of the proposed cell keeps either 0V or the floating state at read mode. We propose a clamp circuit for being biased to 0V when the voltage of FSOURCE is in the floating state. In addition, we propose a VPP switching circuit switching between the logic VDD (=1.8V) and the FSOURCE voltage. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's $0.15{\mu}m$ generic process is $359.92{\times}90.98{\mu}m^2$.

NO2 Sensing Characteristics of Si MOSFET Gas Sensor Based on Thickness of WO3 Sensing Layer

  • Jeong, Yujeong;Hong, Seongbin;Jung, Gyuweon;Jang, Dongkyu;Shin, Wonjun;Park, Jinwoo;Han, Seung-Ik;Seo, Hyungtak;Lee, Jong-Ho
    • Journal of Sensor Science and Technology
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    • v.29 no.1
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    • pp.14-18
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    • 2020
  • This study investigates the nitrogen dioxide (NO2) sensing characteristics of an Si MOSFET gas sensor with a tungsten trioxide (WO3) sensing layer deposited using the sputtering method. The Si MOSFET gas sensor consists of a horizontal floating gate (FG) interdigitated with a control gate (CG). The WO3 sensing layer is deposited on the interdigitated CG-FG of a field effect transistor(FET)-type gas sensor platform. The sensing layer is deposited with different thicknesses of the film ranging from 100 nm to 1 ㎛ by changing the deposition times during the sputtering process. The sensing characteristics of the fabricated gas sensor are measured at different NO2 concentrations and operating temperatures. The response of the gas sensor increases as the NO2 concentration and operating temperature increase. However, the gas sensor has an optimal performance at 180℃ considering both response and recovery speed. The response of the gas sensor increases significantly from 24% to 138% as the thickness of the sensing layer increases from 100 nm to 1 ㎛. The sputtered WO3 film consists of a dense part and a porous part. As reported in previous work, the area of the porous part of the film increases as the thickness of the film increases. This increased porous part promotes the reaction of the sensing layer with the NO2 gas. Consequently, the response of the gas sensor increases as the thickness of the sputtered WO3 film increases.

A Study on Characteristics of Jinsatak(陳士鐸)'s Clinic Theory (진사탁(陳士鐸) 임상 이론의 특징에 관한 연구)

  • Jeong, Kyung-Ho;Kim, Ki-Wook;Park, Hyun-Guk
    • Journal of Korean Medical classics
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    • v.22 no.3
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    • pp.31-51
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    • 2009
  • The characteristics of Jin's ideas on clinic theory can be arranged as follows. 1. Jin emphasized warming and tonifying[溫補] in treatment and the part that shows this the best is the taking care of[調理] the Vital gate[命門], kidney, liver, and spleen. His ideas were based on his understanding of a human life's origin, and was influenced by Seolgi(薛己), Joheon-ga(趙獻可) and Janggaebin(張介賓)'s Vital gate and source Gi theory(元氣說) so scholastically, he has that in common with them but was later criticized by later doctors such as Oksamjon(玉三尊) as an 'literary doctor(文字醫)' who followed the ideas of "Uigwan(醫貫)". 2. The warming and tonifying school[溫補學派], who were influenced by Taoism, said in their theory of disease outbreak[發病學說] that since one must not hurt one's Yin essence and Yang fire [陰精陽火] there is more deficiency than excess, so that was why they used tonifying methods. Jin was also like them and this point of view is universal in internal medicine, gynecology, pediatric medicine and surgery and so on. 3. Jin, who saw the negative form of pulse diagnosis[診脈] emphasized following symptoms over pulse diagnosis using the spirit of ‘finding truth based on truth[實事求是]' in "Maekgyeolcheonmi(脈訣闡微)", but emphasized 'the combination of pulse and symptoms[脈證合參]'. He understood pulse diagnosis as a defining tool for symptoms, and in "Seoksilbirok(石室秘錄)" simplified pulse diagnosis into 10 methods : floating/sunken(浮沉), slow/fast(遲數), large/fine(大小), vacuous/replete(虛實) and slippery/rough(滑澀). 4. Jin used 'large formulas(大方)' a lot that usually featured a large dose, and in " Bonchosinpyeon(本草新編)" he thought of the seven formulas(七方) and ten preparations(十劑) as the standard when using medicine. He did away with old customs and presented a 'new(新)' and 'extra(奇)' point of view. He especially used a lot of Insam(人蔘) when tonifying Gi and Geumeunhwa(金銀花) when treating sores and ulcers. 5. In the area of surgery Jin gave priority to the early finding and treatment of disease with internal treatment[內治] and was against the overuse of acupuncture. However records of surgical measures in a special situation like lung abscesses(肺癰) and liver abscesses(肝癰), and anesthetic measures using 'Manghyeongju(忘形酒)' and 'Singoiyak(神膏異藥)' and opening the abdomen or skull, and organ transplants using a dog's tongue are important data. 6. Jin stated the diseases of Gi and blood broadly. Especially in the principles of treating blood, blood diseases had to be forwarded[順] and Gi regulation[理氣] was the number one priority and stated the following two treatments. First, in "Jeonggiinhyeolpyeon(精氣引血篇)" of volume 6 of "Oegyeongmieon(外經微言)", for the rules for treating blood he stated the pattern identification of finding Gi in blood and blood in Gi. Second, he emphasized Gi regulation(理氣) in blood diseases and stated that the Gi must be tonifyed after finding the source of the loss of blood.

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Study of Data Retention Characteristics with surrounding cell's state in a MLC NAND Flash Memory (멀티 레벨 낸드 플레쉬 메모리에서 주변 셀 상태에 따른 데이터 유지 특성에 대한 연구)

  • Choi, Deuk-Sung;Choi, Sung-Un;Park, Sung-Kye
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.4
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    • pp.239-245
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    • 2013
  • The data retention characteristics depending on neighbor cell's threshold voltage (Vt) in a multilevel NAND flash memory is studied. It is found that a Vt shift (${\Delta}Vt$) of the noted cell during a thermal retention test is increased as the number of erase-state (lowest Vt state) cells surrounding the noted cell increases. It is because a charge loss from a floating gate is originated from not only intrinsic mechanism but also lateral electric field between the neighboring cells. From the electric field simulation, we can find that the electric field is increased and it results in the increased charge loss as the device is scaled down.