• Proceedings of the KWS Conference
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• 2005.06a
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• pp.40-42
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• 2005

• Journal of Welding and Joining
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• v.26 no.1
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• pp.31-36
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• 2008

• Journal of Welding and Joining
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• v.25 no.2
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• pp.6-15
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• 2007

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.10a
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• pp.497-498
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• 2006

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.218-220
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• 2006

Sn-3.0Ag-0.5Cu solder is widely used as micro-joining materials of flip chip package(FCP) because of the fact that it causes less dissolution and has good thermal fatigue property. However, compared with ternary electroplating in the manufacturing process, binary electroplating is still used in industrial field because of easy to make plating solution and composition control. The objective of this research is to fabricate Sn-3.0Ag-0.5Cu solder bumping having accurate composition. The ternary Sn-3.0Ag-0.5Cu solder bumping could be made on a Cu pad by sequent binary electroplating of Sn-Cu and Sn-Ag. Composition of the solder was estimated by EDS and ICP-OES. The thickness of the bump was measured using SEM and the microstructure of intermetallic-compounds(IMCs) was observed by SEM and EDS. From the results, contents of Ag and CU found to be at $2.7{\pm}0.3wt%\;and\;0.4{\pm}0.1wt%$, respectively.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Journal of the Korean Ceramic Society
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• v.50 no.3
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• pp.238-243
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• 2013

We investigated the effect of Pb-metal filler added to a hybrid paste(PbO-$Bi_2O_3-B_2O_3$-ZnO glass frit and Pb-powder), for joining flip-chip sat lower temperatures than normal. The glass transition temperature was detected at $250^{\circ}C$ and the softening point occurred at $330^{\circ}C$. As the temperature increased, the specific density decreased due to the volatility of the Pb-metal and boron component in the glass. When the glass was heat-treated at $350^{\circ}C$ for 5 min, XRD results revealed a crystalline $Pb_4Bi_3B_7O_{19}$ phase that had been initiated by the addition of Pb-filler in the hybrid paste. The addition of the Pb-metal filler caused are action between the Pb-metal and glass that accelerated the formation of the liquid phase. The liquid phase that formed, promoted bonding between the flip-chip substrate sat lower temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.158-158
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• 2008

모바일 정보통신기기를 중심으로 실장모듈의 초소형화, 고집적화로 인해 접속단자의 피치가 점점 미세화 됨에 따라 플립칩 본딩용 접착제에 함유되는 무기충전제인 실리카 필러의 크기도 미세화되고 있다. 본 연구에서는 NCP (non-conductive paste)의 실리카 필러의 크기가 COB(chip-on-board) 플립칩 패키지의 신뢰성에 미치는 영향을 조사하였다. 실험에 사용된 실리카 필러는 Fused silica 3 종과 Fumed silica 3종이며 response surface 실험계획법에 따라 혼합하여 최적의 혼합비를 정하였다. 테스트베드로 사용된 실리콘 다이는 투께 $700{\mu}m$, 면적 5.2$\times$7.2mm로 $50\times50{\mu}m$ 크기의 Au 도금범프를 $100{\mu}m$ 피치, peripheral 방식으로 형성시켰으며, 기판은 패드를 Sn으로 finish 하였다. 기판을 플라즈마 전처리 후 Panasonic FCB-3 플립칩 본더를 이용하여 플립칩 본딩을 수행하였다. 패키지의 신뢰성 평가를 위해 $-40^{\circ}C{\sim}80^{\circ}C$의 열충격시험과 $85^{\circ}C$/85%R.H.의 고온고습시험을 수행하였으며 Die shear를 통한 접합 강도와 4-point probe를 통한 접속저항을 측정하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.270-274
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• 2002

We have developed a new COG technique using flip chip solder joining technology for excellent resolution and high quality LCD panels. Using the eutectic Bi-Sn and the eutectic In-Ag solder bumps of 50-80 ${\mu}m$ pitch sizes, a ultrafine interconnection between IC and glass substrate was successfully made at or below $160^{\circ}C$. The contact resistance and reliability of Bi-Sn solder joint showed the superiority over the conventional ACF bonding.

• Korean Journal of Metals and Materials
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• v.47 no.7
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• pp.447-453
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• 2009

Isotropic conductive adhesives (ICAs) have been used or considered as an interconnect material for radio frequency identification (RFID) inlays or other flip chip assemblies due to the advantages of having a low temperature and high-speed bonding. In this work, the curing properties of commercial ICAs for the RFID tag application and the signal transmission in conductive lines that contained the ICA joints were evaluated as a function of the degree of cure at 900 MHz frequency range. The ICAs showed adequate signal transmission only after the curing process passed over the critical time. It was also found that the insertion loss of signal was more dependent on the contact states of Ag fillers in the bondline in preference to the electrical resistance of the ICA itself.