• 대한전자공학회논문지SD
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• 제41권6호
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• pp.1-7
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• 2004

본 논문에서는 2차원 양자 역학적 모델링 및 시뮬레이션(quantum mechanical modeling and simulation)으로써, 자기정렬 이중게이츠 구조(self-aligned double-gate structure)인 FinFET에 관하여 결합된 푸아송-슈뢰딩거 방정식(coupled Poisson and Schrodinger equations)를 셀프-컨시스턴트(self-consistent)한 방법으로 해석하는 수치적 모델을 제안한다. 시뮬레이션은 게이트 길이(Lg)를 10에서 80nm까지, 실리콘 핀 두께($T_{fin}$)를 10에서 40nm까지 변화시켜가며 시행되었다. 시뮬레이션의 검증을 위한 전류-전압 특성을 실험 결과값과 비교하였으며, 문턱 전압 이하 기울기(subthreshold swing), 문턱 전압 롤-오프(thresholdvoltage roll-off), 그리고 드레인 유기 장벽 감소(drain induced barrier lowering, DIBL)과 같은 파라미터를 추출함으로써 단채널 효과를 줄이기 위한 소자 최적화를 시행하였다. 또한, 고전적 방법과 양자 역학적 방법의 시뮬레이션 결과를 비교함으로써,양자 역학적 해석의 필요성을 확인하였다. 본 연구를 통해서, FinFET과 같은 구조가 단채널 효과를 줄이는데 이상적이며, 나노-스케일 소자 구조를 해석함에 있어 양자 역학적 시뮬레이션이 필수적임을 알 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.51-55
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• 2007

This paper investigates the subthreshold behavior of Fin Field Effect Transistor (FinFET). The FinFET is considered to be an alternate MOSFET structure for the deep sub-micron regime, having excellent device characteristics. As the channel length decreases, the study of subthreshold behavior of the device becomes critically important for successful design and implementation of digital circuits. An accurate analysis of subthreshold behavior of FinFET was done by simulating the device in a 3D process and device simulator, Taurus. The subthreshold behavior of FinFET, was measured using a parameter called S-factor which was obtained from the $In(I_{DS})\;-\;V_{GS}$ characteristics. The value of S-factor of devices of various fin dimensions with channel length $L_g$ in the range of 20 nm - 50 nm and with the fin width $T_{fin}$ in the range of 10 nm - 40 nm was calculated. It was observed that for devices with longer channel lengths, the value of S-factor was close to the ideal value of 60 m V/dec. The S-factor increases exponentially for channel lengths, $L_g\;<\;1.5\;T_{fin}$. Further, for a constant $L_g$, the S factor was observed to increase with $T_{fin}$. An empirical relationship between S, $L_g$ and $T_{fin}$ was developed based on the simulation results, which could be used as a rule of thumb for determining the S-factor of devices.

• 한국전기전자재료학회논문지
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• 제20권5호
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.358-365
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• 2016

We propose a novel application of random forest, a machine learning-based general classification algorithm, to analyze the influence of design attributes on the silicon-to-SPICE (S2S) gap. To improve modeling accuracy, we introduce magnification of learning data as well as randomization for the counting of design attributes to be used for each tree in the forest. From the automatically generated decision trees, we can extract the so-called importance and impact indices, which identify the most significant design attributes determining the S2S gap. We apply the proposed method to actual silicon data, and observe that the identified design attributes show a clear trend in the S2S gap. We finally unveil 10nm key fin-shaped field effect transistor (FinFET) structures that result in a large S2S gap using the measurement data from 10nm test vehicles specialized for model-hardware correlation.

• 융합정보논문지
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• 제11권9호
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• pp.124-129
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• 2021

본 연구는 시간-보간법을 적용한 FLASH analog-to-digital converter (ADC)에 관한 것이다. 시간-보간법은 기존의 FLASH ADC에서 요구되는 전압영역 비교기의 개수를 줄일 수 있으며 이 따른 전력 소모 및 칩 면적의 절약을 기대할 수 있다. 본 연구에서는 5-bit, 즉 31개의 양자화 레벨을 갖는 ADC를 설계 및 구현하였으며, 16개의 양자화 레벨은 기존의 전압영역 비교기 방식을 유지하고, 나머지 15개의 양자화 레벨은 시간영역 비교기를 통하여 처리되도록 구성하여, 기존 5-bit FLASH ADC 대비 전압영역 비교기의 숫자를 48.4% 줄일 수 있었다. 시제품은 14 nm Fin Field-effect transistor (FinFET) 공정으로 제작되었으며 구현면적은 0.0024 mm², 전력소모는 0.8 V 전원전압에서 0.82 mW로 측정되었으며, 400 MS/s의 변환속도 21 MHz 정현파 입력에 대하여 ADC는 28.03 dB의 신호-대-잡음비 (SNDR), 즉 4.36 유효비트(ENOB)의 성능을 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• 융합정보논문지
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• 제11권7호
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• pp.104-110
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• 2021

본 핀 채널 전계 효과 트랜지스터에서 낮은 소스/드레인 직렬 저항을 위한 새로운 선택적 산화 방식을 제안하였다. 이 방법을 이용하면, gate-all-around 구조와 점진적으로 증가되는 형태의 소스/드레인 확장영역을 갖는 핀 채널 MOSFET를 얻을 수 있다. 제안된 트랜지스터는 비교 소자에 비해 70% 이상의 소스/드레인 직렬 저항의 감소를 얻을 수 있다. 또한, 제안된 소자는 단채널 효과를 억제하면서도 높은 구동 전류와 전달컨덕턴스 특징을 보인다. 제작된 소자의 포화전류, 최대 선형 전달컨덕턴스, 최대 포화 전달컨덕턴스, subthreshold swing, 및 DIBL은 각각 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, 62 mV/V의 값을 갖는다.

• 한국전기전자재료학회논문지
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• 제33권3호
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• pp.169-172
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• 2020

In this paper, the effect of hot carrier injection on an n-bulk fin field-effect transistor (FinFET) is analyzed. The hot carrier injection method is applied to determine the performance change after injection in two ways, channel hot electron (CHE) and drain avalanche hot carrier (DAHC), which have the greatest effect at room temperature. The optimum condition for CHE injection is V_G=V_D, and the optimal condition for DAHC injection can be indirectly confirmed by measuring the peak value of the substrate current. Deterioration by DAHC injection affects not only hot electrons formed by impact ionization, but also hot holes, which has a greater impact on reliability than CHE. Further, we test the amount of drain voltage that can be withstood, and extracted the lifetime of the device. Under CHE injection conditions, the drain voltage was able to maintain a lifetime of more than 10 years at a maximum of 1.25 V, while DAHC was able to achieve a lifetime exceeding 10 years at a 1.05-V drain voltage, which is 0.2 V lower than that of CHE injection conditions.