• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.45-50
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• 2013

Recently, as the market for SMART TV expands, the camera is embedded for providing various user experience. However, this leads to occurrence of camera failure due to TV power up sequence problem, which are usually not detectable in conventional test equipments. Although the failure-detection can be possible by re-generating control signals for audio interface with new equipment, it is expensive and also requires much time to test. In this paper, for SMART TV, FPGA(Field Programmable Gate Array)-based failure-detection system is proposed which can lead to reduction of both cost and time for test.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.2
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• pp.287-293
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• 2018

Field Programmable Gate Array (FPGA) is widely used in a variety of fields because of its ability to be programmed as desired. However, when an externally implemented program is loaded on FPGA in the form of a bitstream, there is a possibility that hardware Trojans which cause malfunctions or leak information may be included. For this reason, bitstream reverse engineering is essential, and therefore related research has been conducted, such as BIL. In this paper, we analyze the BIL bitstream reverse engineering tool, which is the most representative algorithm, regarding its performance and limitations.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Journal of Korea Multimedia Society
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• v.11 no.10
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• pp.1460-1470
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• 2008

As the performance of recent mobile systems increases, a vector graphic has been implemented to represent various types of dynamic menus, mails, and two-dimensional maps. This paper proposes a hardware accelerator for open vector graphics (OpenVG), which is widely used for two-dimensional vector graphics. We analyze the specifications of an OpenVG and divide the OpenVG into several functions suitable for hardware implementation. The proposed hardware accelerator is implemented on a field programmable gate array (FPGA) board using hardware description language (HDL) and is about four times faster than an Alex processor.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1171-1177
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• 2002

In this paper, we proposed a high speed IP(Internet Protocol) packet forwarding engine of ATM(Asynchronous Transfer Mode) based label edge routers for POS(Packet over SONET) interface. The forwarding engine uses TCAM(Ternary Content Addressable Memory) for high performance lookup processing of the packet received from POS interface. We have accomplished high speed IP packet forwarding in hardware by implementing the functions of high speed IP header Processing and lookup control into FPGA(Field Programmable Gate Array). The proposed forwarding engine has the functions of label edge routers as the lookup controller supports MPLS(Multiprotocol Label Switching) packet processing functionality.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.669-679
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• 2013

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.2
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• pp.131-137
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• 2005

Protective relays provide important features to electrical power systems for protecting against faults and consequent short circuits. This research presents a novel VLSI design of the digital protective relay, which overcomes today's uP/DSP-based relays. This design features good cancellation of DC/k-th harmonic components, noticeable not performance and flexible Protection behavior in the minimized core area The proposed design was successfully implemented by a FPGA(Field Programmable Gate Array) device and can concurrently process over 16KSPS at less $0.03[\%]$ error rate.

• 전자공학회논문지 IE
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• v.48 no.3
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• pp.20-25
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• 2011

We developed a method of accelerating the operation speed of communication systems for SDR(Software Defined Radio) systems in WiBro environment. In this paper, we propose a new scheme of using GPU(Graphics Processing Unit) for implementing the communication system which perform with the functionality of SDR. In general, communication systems is made by DSP(Digital Signalling Processor) or FPGA(Field Programmable Gate Array). However, in this case, there are exist the problem of implementation and debugging caused by each CPU characteristic. The GPU is optimized for vector processing because it usually consists of multiple processors and each processor in GPU is composed of a set of threads. We also developed Framework to use GPU and CPU resources effectively for reducing the operation time. From the various simulation, it is confirmed that GPU system have good performance in WiBro system.

• Convergence Security Journal
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• v.17 no.2
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• pp.41-51
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• 2017

The explosive increase in the range of Internet usage gradually makes the speed and capacity of network high-speed, rapidly evolving it into mass storage. Accordingly, network equipment such as switch and router are coping with it through hardware-based rapid technological evolution, but as the technological development of the most basic and essential network security system in the hyper-connected society requires frequent alterations and updates about the security issues and signatures of tens of thousands, so it is not easy to overcome the technical limitations based on the software. In this paper, to improve problems in installing and operating such anti-DDoS devices, we propose a Hi-DPI algorithm best reflecting the hardware characteristics and parallel processing characteristics of FPGA (Field Programmable Gate Array), and would verify the practicality.