A Study on the BIL Bitstream Reverse-Engineering Tool-Chain Analysis |
Yoon, Junghwan
(Information Security Lab., Graduation School of Information, Yonsei University)
Seo, Yezee (Information Security Lab., Graduation School of Information, Yonsei University) Kim, Hoonkyu (Agency for Defense Development) Kwon, Taekyoung (Information Security Lab., Graduation School of Information, Yonsei University) |
1 | T. Todman, G. Constant S. Wilton, O. Mencer, W. Luk, and P. Cheung, "Reconfigurable computing: architectures and design methods," Computers and Digital Techniques, Vol. 152, No. 2, pp. 193-207, Mar. 2005. DOI |
2 | L. Sekanina, "Towards Evolvable IP Cores for FPGAs," In Proc. NASA/DoD Conference on Evolvable Hardware, pp. 145, Jul. 2003. |
3 | S. Mal-Sarkar, R. Karam, S. Narasimhan, A. Ghosh, A. krishna, and S. Bhunia, "Design and Validation for FPGA Trust under Hardware Trojan Attacks," IEEE Transactions on Multi-Scale Computing Systems, Vol. 2, No. 3, pp. 186-198, Jun. 2016. DOI |
4 | J.B. Note and E. Rannaud, "From the bitstream to the netlist," In Proc. the 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 264-271, Feb. 2008. |
5 | F. Benz, A. Seffrin, and S.A. Huss, "Bil: A tool-chain for bitsream reverse-en- gineering," In Proc. International Conference on Field Programmable Logic and Applications (FPL), pp. 735-738, Aug. 2012. |
6 | Z. Ding, Q. Wu, Y. Zhang, and L. Zhu, "Deriving an NCD file from an FPGA bit- stream: Methodology, architecture and evaluation," Microprocessors and Microsystems, Vol. 37, No. 3, pp. 299-312, May. 2013. DOI |
7 | C. Beckhoff, D. Koch and J. Torresen, "The Xilinx Design Language (XDL): Tutorial and use cased," In Proc. International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), pp. 1-8, Jun. 2011. |
8 | Xilinx Inc., "Virtex-5 Family Overview," https://www.xilinx.com/support/documentation/data_sheets/ds100.pdf, Aug. 2015. |